📄 mk10n512md100.h
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/*! \} */ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/*! Peripheral ADC0 base address */
#define ADC0_BASE (0x4003B000u)
/*! Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
/*! Peripheral ADC1 base address */
#define ADC1_BASE (0x400BB000u)
/*! Peripheral ADC1 base pointer */
#define ADC1 ((ADC_Type *)ADC1_BASE)
/*! \} */ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AIPS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*! \addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer */
/*! \{ */
/*! AIPS - Register Layout Typedef */
typedef struct {
__IO uint32_t MPRA; /*!< Master Privilege Register A, offset: 0x0 */
uint8_t RESERVED_0[28];
__IO uint32_t PACRA; /*!< Peripheral Access Control Register, offset: 0x20 */
__IO uint32_t PACRB; /*!< Peripheral Access Control Register, offset: 0x24 */
__IO uint32_t PACRC; /*!< Peripheral Access Control Register, offset: 0x28 */
__IO uint32_t PACRD; /*!< Peripheral Access Control Register, offset: 0x2C */
uint8_t RESERVED_1[16];
__IO uint32_t PACRE; /*!< Peripheral Access Control Register, offset: 0x40 */
__IO uint32_t PACRF; /*!< Peripheral Access Control Register, offset: 0x44 */
__IO uint32_t PACRG; /*!< Peripheral Access Control Register, offset: 0x48 */
__IO uint32_t PACRH; /*!< Peripheral Access Control Register, offset: 0x4C */
__IO uint32_t PACRI; /*!< Peripheral Access Control Register, offset: 0x50 */
__IO uint32_t PACRJ; /*!< Peripheral Access Control Register, offset: 0x54 */
__IO uint32_t PACRK; /*!< Peripheral Access Control Register, offset: 0x58 */
__IO uint32_t PACRL; /*!< Peripheral Access Control Register, offset: 0x5C */
__IO uint32_t PACRM; /*!< Peripheral Access Control Register, offset: 0x60 */
__IO uint32_t PACRN; /*!< Peripheral Access Control Register, offset: 0x64 */
__IO uint32_t PACRO; /*!< Peripheral Access Control Register, offset: 0x68 */
__IO uint32_t PACRP; /*!< Peripheral Access Control Register, offset: 0x6C */
} AIPS_Type;
/* ----------------------------------------------------------------------------
-- AIPS Register Masks
---------------------------------------------------------------------------- */
/*! \addtogroup AIPS_Register_Masks AIPS Register Masks */
/*! \{ */
/* MPRA Bit Fields */
#define AIPS_MPRA_MPL5_MASK 0x100u
#define AIPS_MPRA_MPL5_SHIFT 8
#define AIPS_MPRA_MTW5_MASK 0x200u
#define AIPS_MPRA_MTW5_SHIFT 9
#define AIPS_MPRA_MTR5_MASK 0x400u
#define AIPS_MPRA_MTR5_SHIFT 10
#define AIPS_MPRA_MPL2_MASK 0x100000u
#define AIPS_MPRA_MPL2_SHIFT 20
#define AIPS_MPRA_MTW2_MASK 0x200000u
#define AIPS_MPRA_MTW2_SHIFT 21
#define AIPS_MPRA_MTR2_MASK 0x400000u
#define AIPS_MPRA_MTR2_SHIFT 22
#define AIPS_MPRA_MPL1_MASK 0x1000000u
#define AIPS_MPRA_MPL1_SHIFT 24
#define AIPS_MPRA_MTW1_MASK 0x2000000u
#define AIPS_MPRA_MTW1_SHIFT 25
#define AIPS_MPRA_MTR1_MASK 0x4000000u
#define AIPS_MPRA_MTR1_SHIFT 26
#define AIPS_MPRA_MPL0_MASK 0x10000000u
#define AIPS_MPRA_MPL0_SHIFT 28
#define AIPS_MPRA_MTW0_MASK 0x20000000u
#define AIPS_MPRA_MTW0_SHIFT 29
#define AIPS_MPRA_MTR0_MASK 0x40000000u
#define AIPS_MPRA_MTR0_SHIFT 30
/* PACRA Bit Fields */
#define AIPS_PACRA_TP7_MASK 0x1u
#define AIPS_PACRA_TP7_SHIFT 0
#define AIPS_PACRA_WP7_MASK 0x2u
#define AIPS_PACRA_WP7_SHIFT 1
#define AIPS_PACRA_SP7_MASK 0x4u
#define AIPS_PACRA_SP7_SHIFT 2
#define AIPS_PACRA_TP6_MASK 0x10u
#define AIPS_PACRA_TP6_SHIFT 4
#define AIPS_PACRA_WP6_MASK 0x20u
#define AIPS_PACRA_WP6_SHIFT 5
#define AIPS_PACRA_SP6_MASK 0x40u
#define AIPS_PACRA_SP6_SHIFT 6
#define AIPS_PACRA_TP5_MASK 0x100u
#define AIPS_PACRA_TP5_SHIFT 8
#define AIPS_PACRA_WP5_MASK 0x200u
#define AIPS_PACRA_WP5_SHIFT 9
#define AIPS_PACRA_SP5_MASK 0x400u
#define AIPS_PACRA_SP5_SHIFT 10
#define AIPS_PACRA_TP4_MASK 0x1000u
#define AIPS_PACRA_TP4_SHIFT 12
#define AIPS_PACRA_WP4_MASK 0x2000u
#define AIPS_PACRA_WP4_SHIFT 13
#define AIPS_PACRA_SP4_MASK 0x4000u
#define AIPS_PACRA_SP4_SHIFT 14
#define AIPS_PACRA_TP3_MASK 0x10000u
#define AIPS_PACRA_TP3_SHIFT 16
#define AIPS_PACRA_WP3_MASK 0x20000u
#define AIPS_PACRA_WP3_SHIFT 17
#define AIPS_PACRA_SP3_MASK 0x40000u
#define AIPS_PACRA_SP3_SHIFT 18
#define AIPS_PACRA_TP2_MASK 0x100000u
#define AIPS_PACRA_TP2_SHIFT 20
#define AIPS_PACRA_WP2_MASK 0x200000u
#define AIPS_PACRA_WP2_SHIFT 21
#define AIPS_PACRA_SP2_MASK 0x400000u
#define AIPS_PACRA_SP2_SHIFT 22
#define AIPS_PACRA_TP1_MASK 0x1000000u
#define AIPS_PACRA_TP1_SHIFT 24
#define AIPS_PACRA_WP1_MASK 0x2000000u
#define AIPS_PACRA_WP1_SHIFT 25
#define AIPS_PACRA_SP1_MASK 0x4000000u
#define AIPS_PACRA_SP1_SHIFT 26
#define AIPS_PACRA_TP0_MASK 0x10000000u
#define AIPS_PACRA_TP0_SHIFT 28
#define AIPS_PACRA_WP0_MASK 0x20000000u
#define AIPS_PACRA_WP0_SHIFT 29
#define AIPS_PACRA_SP0_MASK 0x40000000u
#define AIPS_PACRA_SP0_SHIFT 30
/* PACRB Bit Fields */
#define AIPS_PACRB_TP7_MASK 0x1u
#define AIPS_PACRB_TP7_SHIFT 0
#define AIPS_PACRB_WP7_MASK 0x2u
#define AIPS_PACRB_WP7_SHIFT 1
#define AIPS_PACRB_SP7_MASK 0x4u
#define AIPS_PACRB_SP7_SHIFT 2
#define AIPS_PACRB_TP6_MASK 0x10u
#define AIPS_PACRB_TP6_SHIFT 4
#define AIPS_PACRB_WP6_MASK 0x20u
#define AIPS_PACRB_WP6_SHIFT 5
#define AIPS_PACRB_SP6_MASK 0x40u
#define AIPS_PACRB_SP6_SHIFT 6
#define AIPS_PACRB_TP5_MASK 0x100u
#define AIPS_PACRB_TP5_SHIFT 8
#define AIPS_PACRB_WP5_MASK 0x200u
#define AIPS_PACRB_WP5_SHIFT 9
#define AIPS_PACRB_SP5_MASK 0x400u
#define AIPS_PACRB_SP5_SHIFT 10
#define AIPS_PACRB_TP4_MASK 0x1000u
#define AIPS_PACRB_TP4_SHIFT 12
#define AIPS_PACRB_WP4_MASK 0x2000u
#define AIPS_PACRB_WP4_SHIFT 13
#define AIPS_PACRB_SP4_MASK 0x4000u
#define AIPS_PACRB_SP4_SHIFT 14
#define AIPS_PACRB_TP3_MASK 0x10000u
#define AIPS_PACRB_TP3_SHIFT 16
#define AIPS_PACRB_WP3_MASK 0x20000u
#define AIPS_PACRB_WP3_SHIFT 17
#define AIPS_PACRB_SP3_MASK 0x40000u
#define AIPS_PACRB_SP3_SHIFT 18
#define AIPS_PACRB_TP2_MASK 0x100000u
#define AIPS_PACRB_TP2_SHIFT 20
#define AIPS_PACRB_WP2_MASK 0x200000u
#define AIPS_PACRB_WP2_SHIFT 21
#define AIPS_PACRB_SP2_MASK 0x400000u
#define AIPS_PACRB_SP2_SHIFT 22
#define AIPS_PACRB_TP1_MASK 0x1000000u
#define AIPS_PACRB_TP1_SHIFT 24
#define AIPS_PACRB_WP1_MASK 0x2000000u
#define AIPS_PACRB_WP1_SHIFT 25
#define AIPS_PACRB_SP1_MASK 0x4000000u
#define AIPS_PACRB_SP1_SHIFT 26
#define AIPS_PACRB_TP0_MASK 0x10000000u
#define AIPS_PACRB_TP0_SHIFT 28
#define AIPS_PACRB_WP0_MASK 0x20000000u
#define AIPS_PACRB_WP0_SHIFT 29
#define AIPS_PACRB_SP0_MASK 0x40000000u
#define AIPS_PACRB_SP0_SHIFT 30
/* PACRC Bit Fields */
#define AIPS_PACRC_TP7_MASK 0x1u
#define AIPS_PACRC_TP7_SHIFT 0
#define AIPS_PACRC_WP7_MASK 0x2u
#define AIPS_PACRC_WP7_SHIFT 1
#define AIPS_PACRC_SP7_MASK 0x4u
#define AIPS_PACRC_SP7_SHIFT 2
#define AIPS_PACRC_TP6_MASK 0x10u
#define AIPS_PACRC_TP6_SHIFT 4
#define AIPS_PACRC_WP6_MASK 0x20u
#define AIPS_PACRC_WP6_SHIFT 5
#define AIPS_PACRC_SP6_MASK 0x40u
#define AIPS_PACRC_SP6_SHIFT 6
#define AIPS_PACRC_TP5_MASK 0x100u
#define AIPS_PACRC_TP5_SHIFT 8
#define AIPS_PACRC_WP5_MASK 0x200u
#define AIPS_PACRC_WP5_SHIFT 9
#define AIPS_PACRC_SP5_MASK 0x400u
#define AIPS_PACRC_SP5_SHIFT 10
#define AIPS_PACRC_TP4_MASK 0x1000u
#define AIPS_PACRC_TP4_SHIFT 12
#define AIPS_PACRC_WP4_MASK 0x2000u
#define AIPS_PACRC_WP4_SHIFT 13
#define AIPS_PACRC_SP4_MASK 0x4000u
#define AIPS_PACRC_SP4_SHIFT 14
#define AIPS_PACRC_TP3_MASK 0x10000u
#define AIPS_PACRC_TP3_SHIFT 16
#define AIPS_PACRC_WP3_MASK 0x20000u
#define AIPS_PACRC_WP3_SHIFT 17
#define AIPS_PACRC_SP3_MASK 0x40000u
#define AIPS_PACRC_SP3_SHIFT 18
#define AIPS_PACRC_TP2_MASK 0x100000u
#define AIPS_PACRC_TP2_SHIFT 20
#define AIPS_PACRC_WP2_MASK 0x200000u
#define AIPS_PACRC_WP2_SHIFT 21
#define AIPS_PACRC_SP2_MASK 0x400000u
#define AIPS_PACRC_SP2_SHIFT 22
#define AIPS_PACRC_TP1_MASK 0x1000000u
#define AIPS_PACRC_TP1_SHIFT 24
#define AIPS_PACRC_WP1_MASK 0x2000000u
#define AIPS_PACRC_WP1_SHIFT 25
#define AIPS_PACRC_SP1_MASK 0x4000000u
#define AIPS_PACRC_SP1_SHIFT 26
#define AIPS_PACRC_TP0_MASK 0x10000000u
#define AIPS_PACRC_TP0_SHIFT 28
#define AIPS_PACRC_WP0_MASK 0x20000000u
#define AIPS_PACRC_WP0_SHIFT 29
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