tcontroller_test.v

来自「一个用verilog语言编写的用来模拟交通信号灯的程序」· Verilog 代码 · 共 28 行

//------   this design is for test_bench   --------//
//------   

`timescale 1ns/100ps
`define clk_cycle 50
module Tcontroller_test;
	reg clk,reset;
	wire green,yellow,red;
	wire green2,yellow2,red2;
	
	always 
		#`clk_cycle clk = ~clk;
	
	initial
		begin
			clk = 0;
			reset = 0;
			#70 
			reset = 1;
			#30 
			reset = 0;
			#10000
			$stop; 
		end
//	Tcontroller  t1(green,yellow,red,clk,reset);
	Tcontroller2 t2(green2,yellow2,red2,clk,(~reset));
	
endmodule