📄 ad9850.lst
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01B5 75347F 224 mov ZLG_MOVE_BUFF,#07FH
01B8 753288 225 mov ZLG_SEND_BUF,#88H
01BB 1202FB 226 lcall zlg_send
01BE 75327F 227 mov ZLG_SEND_BUF,#01111111B
01C1 1202FB 228 lcall zlg_send
01C4 D280 229 setb ZLG_CS
01C6 120096 230 lcall zlg_display
01C9 231 SCAN_KEY_EXIT:
01C9 C0E0 232 push acc
01CB E560 233 mov a,TAG_REFURBISH
01CD B4FF06 234 cjne a,#0FFH,NOT_REFURBISH
01D0 120202 235 lcall parallelism_bit_refurbish
01D3 756000 236 mov TAG_REFURBISH,#00H
01D6 237 NOT_REFURBISH:
01D6 D0E0 238 pop acc
01D8 22 239 ret
240 ;*****************************************************************************
01D9 241 move_left:
01D9 C0E0 242 push acc
01DB E534 243 mov a,ZLG_MOVE_BUFF
01DD 23 244 RL a
01DE F534 245 mov ZLG_MOVE_BUFF,a
01E0 1201F3 246 lcall zlg_move
01E3 D0E0 247 pop acc
01E5 22 248 ret
249 ;***************************************************************************
01E6 250 move_right:
01E6 C0E0 251 push acc
01E8 E534 252 mov a,ZLG_MOVE_BUFF
01EA 03 253 RR a
01EB F534 254 mov ZLG_MOVE_BUFF,a
01ED 1201F3 255 lcall zlg_move
A51 MACRO ASSEMBLER AD9850 08/26/2007 16:12:21 PAGE 5
01F0 D0E0 256 pop acc
01F2 22 257 ret
258 ;****************************************************************************
01F3 259 zlg_move:
01F3 753288 260 mov ZLG_SEND_BUF,#88H
01F6 1202FB 261 lcall zlg_send
01F9 853432 262 mov ZLG_SEND_BUF,ZLG_MOVE_BUFF
01FC 1202FB 263 lcall zlg_send
01FF D280 264 setb ZLG_CS
0201 22 265 RET
266 ;***************************************************************************
0202 267 parallelism_bit_refurbish: ;move left and right after refurbish every bit
0202 C0E0 268 push acc
0204 E534 269 mov a,ZLG_MOVE_BUFF
0206 B47F05 270 cjne a,#01111111B,BIT_H_4
0209 853353 271 mov ZLG_PARA_NUM_H4,ZLG_DECIMAL_BUFF
020C 8036 272 jmp PARA_BIT_EXIT
020E 273 BIT_H_4:
020E B4BF05 274 cjne a,#10111111B,BIT_H_3
0211 853352 275 mov ZLG_PARA_NUM_H3,ZLG_DECIMAL_BUFF
0214 802E 276 jmp PARA_BIT_EXIT
0216 277 BIT_H_3:
0216 B4DF05 278 cjne a,#11011111B,BIT_H_2
0219 853351 279 mov ZLG_PARA_NUM_H2,ZLG_DECIMAL_BUFF
021C 8026 280 jmp PARA_BIT_EXIT
021E 281 BIT_H_2:
021E B4EF05 282 cjne a,#11101111B,BIT_H_1
0221 853350 283 mov ZLG_PARA_NUM_H1,ZLG_DECIMAL_BUFF
0224 801E 284 jmp PARA_BIT_EXIT
0226 285 BIT_H_1:
0226 B4F705 286 cjne a,#11110111B,BIT_L_4
0229 853357 287 mov ZLG_PARA_NUM_L4,ZLG_DECIMAL_BUFF
022C 8016 288 jmp PARA_BIT_EXIT
022E 289 BIT_L_4:
022E B4FB05 290 cjne a,#11111011B,BIT_L_3
0231 853356 291 mov ZLG_PARA_NUM_L3,ZLG_DECIMAL_BUFF
0234 800E 292 jmp PARA_BIT_EXIT
0236 293 BIT_L_3:
0236 B4FD05 294 cjne a,#11111101B,BIT_L_2
0239 853355 295 mov ZLG_PARA_NUM_L2,ZLG_DECIMAL_BUFF
023C 8006 296 jmp PARA_BIT_EXIT
023E 297 BIT_L_2:
023E B4FE03 298 cjne a,#11111110B,PARA_BIT_EXIT
0241 853354 299 mov ZLG_PARA_NUM_L1,ZLG_DECIMAL_BUFF
0244 300 PARA_BIT_EXIT:
0244 D0E0 301 pop acc
0246 22 302 ret
303 ;***************************************************************************
0247 304 count_freg:
0247 C0E0 305 push acc
0249 7B08 306 mov r3,#08H
024B 307 COUNT_LOOP:
024B BB0807 308 cjne r3,#08,COUNT_FREG_99
024E E553 309 mov a,ZLG_PARA_NUM_H4 ;read high bit of four
0250 900470 310 mov dptr,#TAB_FREG_10MHZ ;check the table 10MHZ
0253 8044 311 jmp COUNT_FREG_EXIT
0255 312 COUNT_FREG_99:
0255 BB0707 313 cjne r3,#07,COUNT_FREG_1
0258 E552 314 mov a,ZLG_PARA_NUM_H3 ;read high bit of three
025A 900448 315 mov dptr,#TAB_FREG_1MHZ_TO_9MHZ ;check the table 1MHZ~9MHZ
025D 803A 316 jmp COUNT_FREG_EXIT
025F 317 COUNT_FREG_1:
025F BB0607 318 cjne r3,#06,COUNT_FREG_2
0262 E551 319 mov a,ZLG_PARA_NUM_H2 ;read high bit of two
0264 900420 320 mov dptr,#TAB_FREG_100KHZ_TO_900KHZ;check the table 100KHZ~900KHZ
0267 8030 321 jmp COUNT_FREG_EXIT
A51 MACRO ASSEMBLER AD9850 08/26/2007 16:12:21 PAGE 6
0269 322 COUNT_FREG_2:
0269 BB0507 323 cjne r3,#05,COUNT_FREG_3
026C E550 324 mov a,ZLG_PARA_NUM_H1 ;read high bit of one
026E 9003F8 325 mov dptr,#TAB_FREG_10KHZ_TO_90KHZ ;check the table 10KHZ~90KHZ
0271 8026 326 jmp COUNT_FREG_EXIT
0273 327 COUNT_FREG_3:
0273 BB0407 328 cjne r3,#04,COUNT_FREG_4
0276 E557 329 mov a,ZLG_PARA_NUM_L4 ;read low bit of four
0278 9003D0 330 mov dptr,#TAB_FREG_1KHZ_TO_9KHZ ;check the table 1KHZ~9KHZ
027B 801C 331 jmp COUNT_FREG_EXIT
027D 332 COUNT_FREG_4:
027D BB0307 333 cjne r3,#03,COUNT_FREG_5
0280 E556 334 mov a,ZLG_PARA_NUM_L3 ;read low bit of three
0282 9003A8 335 mov dptr,#TAB_FREG_100HZ_TO_900HZ ;check the table 100HZ~900HZ
0285 8012 336 jmp COUNT_FREG_EXIT
0287 337 COUNT_FREG_5:
0287 BB0207 338 cjne r3,#02,COUNT_FREG_6
028A E555 339 mov a,ZLG_PARA_NUM_L2 ;read low bit of two
028C 900380 340 mov dptr,#TAB_FREG_10HZ_TO_90HZ ;check the table 10HZ~90HZ
028F 8008 341 jmp COUNT_FREG_EXIT
0291 342 COUNT_FREG_6:
0291 BB0105 343 cjne r3,#01,COUNT_FREG_EXIT
0294 E554 344 mov a,ZLG_PARA_NUM_L1 ;read low bit of one
0296 900358 345 mov dptr,#TAB_FREG_0HZ_TO_9HZ ;check the table 1HZ~9HZ
0299 346 COUNT_FREG_EXIT:
0299 75F004 347 mov b,#04
029C A4 348 mul ab ;the freg is bits of 32
029D F561 349 mov CURRENT_ADDRESS,a
350
029F 93 351 movc a,@a+dptr
02A0 F565 352 mov DATA_REGISTER_H2,a
02A2 0561 353 inc CURRENT_ADDRESS
354
02A4 E561 355 mov a,CURRENT_ADDRESS
356
02A6 93 357 movc a,@a+dptr
02A7 F564 358 mov DATA_REGISTER_H1,a
02A9 0561 359 inc CURRENT_ADDRESS
360
02AB E561 361 mov a,CURRENT_ADDRESS
362
02AD 93 363 movc a,@a+dptr
02AE F563 364 mov DATA_REGISTER_L2,a
02B0 0561 365 inc CURRENT_ADDRESS
366
02B2 E561 367 mov a,CURRENT_ADDRESS
02B4 93 368 movc a,@a+dptr
02B5 F562 369 mov DATA_REGISTER_L1,a
370
02B7 1202BF 371 lcall add_freg
02BA DB8F 372 djnz r3,COUNT_LOOP
02BC D0E0 373 pop acc
02BE 22 374 ret
375 ;***************************************************************************
02BF 376 add_freg: ;check the freg table,and add the freg every bits
02BF C0E0 377 push acc
02C1 E544 378 mov a,WORD_FREG_L1
02C3 3562 379 addc a,DATA_REGISTER_L1
02C5 F544 380 mov WORD_FREG_L1,a
381
02C7 E543 382 mov a,WORD_FREG_L2
02C9 3563 383 addc a,DATA_REGISTER_L2
02CB F543 384 mov WORD_FREG_L2,a
385
02CD E542 386 mov a,WORD_FREG_H1
02CF 3564 387 addc a,DATA_REGISTER_H1
A51 MACRO ASSEMBLER AD9850 08/26/2007 16:12:21 PAGE 7
02D1 F542 388 mov WORD_FREG_H1,a
389
02D3 E541 390 mov a,WORD_FREG_H2
02D5 3565 391 addc a,DATA_REGISTER_H2
02D7 F541 392 mov WORD_FREG_H2,a
02D9 D0E0 393 pop acc
02DB 22 394 ret
395 ;****************************************************************************
02DC 396 write_data:
02DC 759000 397 mov p1,#00H ;注意:这三句也不能忘记
02DF C2B1 398 clr W_CLK
02E1 C2B0 399 clr F_QUD
02E3 12033F 400 lcall long_delay
02E6 754000 401 mov 40H,#00H
02E9 7E05 402 mov r6,#05H ;setting data pointer
02EB 7940 403 mov r1,#40H ;data register of address
02ED 404 WRITE_NEXT:
02ED 8790 405 mov p1,@r1 ;
02EF D2B1 406 setb W_CLK ;On the rising edge of this clock,write data in AD9
850
02F1 C2B1 407 clr W_CLK ;clr
02F3 09 408 inc r1
02F4 DEF7 409 djnz r6,WRITE_NEXT
02F6 D2B0 410 setb F_QUD ;40 bits write in
02F8 C2B0 411 clr F_QUD ;clr
02FA 22 412 ret
413 ;******************************************************************************
02FB 414 zlg_send:
02FB 753008 415 mov ZLG_BIT_CNT,#8 ;Set the number of data sended
02FE C280 416 clr ZLG_CS ;Set set ZLG7289 ready,T1
0300 12034A 417 lcall delay_50;T1
418
0303 419 ZLG_SEND_LP:
420 ;Send a bit
0303 8532E0 421 mov acc,ZLG_SEND_BUF
0306 33 422 rlc a
0307 85E032 423 mov ZLG_SEND_BUF,acc
030A 9282 424 mov ZLG_DATA,c
030C 00 425 nop ;Wait for data to ready
030D 00 426 nop
427
030E D281 428 setb ZLG_CLK ;T2
0310 120351 429 lcall delay_8
0313 C281 430 clr ZLG_CLK ;T3
0315 120351 431 lcall delay_8
0318 D530E8 432 djnz ZLG_BIT_CNT,ZLG_SEND_LP ;Loop to next bit
031B C282 433 clr ZLG_DATA
031D 22 434 ret
435 ;*****************************************************************
436 ;Receive a byte to ZLG7289 with higer bit first
031E 437 zlg_receive:
031E 753008 438 mov ZLG_BIT_CNT,#8 ;Set the number of data received
0321 C280 439 clr ZLG_CS ;Set set ZLG7289 ready,T1
0323 12034A 440 lcall delay_50
441
0326 442 ZLG_REC_LP:
443 ;Receive a bit
0326 D281 444 setb ZLG_CLK ;T2
0328 120351 445 lcall delay_8
446
032B A282 447 mov c,ZLG_DATA
032D 8531E0 448 mov acc,ZLG_REC_BUF
0330 33 449 rlc a
0331 85E031 450 mov ZLG_REC_BUF,acc
451
0334 C281 452 clr ZLG_CLK ;T3
A51 MACRO ASSEMBLER AD9850 08/26/2007 16:12:21 PAGE 8
0336 120351 453 lcall delay_8
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