📄 xllp_mmc.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/******************************************************************************
**
** COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
** This software as well as the software described in it is furnished under
** license and may only be used or copied in accordance with the terms of the
** license. The information in this file is furnished for informational use
** only, is subject to change without notice, and should not be construed as
** a commitment by Intel Corporation. Intel Corporation assumes no
** responsibility or liability for any errors or inaccuracies that may appear
** in this document or any software that may be provided in association with
** this document.
** Except as permitted by such license, no part of this document may be
** reproduced, stored in a retrieval system, or transmitted in any form or by
** any means without the express written consent of Intel Corporation.
**
** FILENAME: xllp_MMC.h
**
******************************************************************************/
// note that this will not be in there in the end; this is only for testing purposes
#define MMC_BASE (0x41100000) // MMC Base Register Location
#ifndef __MMC_H__
#define __MMC_H__
#include "xllp_defs.h"
//#include "xllp_gpio.h"
//#include "xllp_clock.h"
/**
MMC Register Definitions
**/
typedef struct
{
XLLP_VUINT32_T MMC_STRPCL; /* Control to start/stop mmc/sd clock */
XLLP_VUINT32_T MMC_STAT; /* status register*/
XLLP_VUINT32_T MMC_CLKRT; /* clock rate */
XLLP_VUINT32_T MMC_SPI; /* SPI mode control bits */
XLLP_VUINT32_T MMC_CMDAT; /* command/response/data sequence control */
XLLP_VUINT32_T MMC_RESTO; /* expected response timout */
XLLP_VUINT32_T MMC_RDTO; /* expected data read timeout */
XLLP_VUINT32_T MMC_BLKLEN; /* block length of data transaction */
XLLP_VUINT32_T MMC_NUMBLK; /* number of block for block mode */
XLLP_VUINT32_T MMC_PRTBUF; /* partial mmc_txfifo written */
XLLP_VUINT32_T MMC_I_MASK; /* interrupt mask */
XLLP_VUINT32_T MMC_I_REG; /* interrupt register */
XLLP_VUINT32_T MMC_CMD; /* index of current command */
XLLP_VUINT32_T MMC_ARGH; /* MSW part of the current command arg */
XLLP_VUINT32_T MMC_ARGL; /* LSW p art of the current command arg */
XLLP_VUINT32_T MMC_RES; /* response fifo */
XLLP_VUINT32_T MMC_RXFIFO; /* receive fifo for single byte */
XLLP_VUINT32_T MMC_TXFIFO; /* transmit fifo for single byte */
XLLP_VUINT32_T MMC_RESERVED1[33]; /* reserved for different fifo */
XLLP_VUINT32_T SD_CMDAT; /* SD CMDAT register */
XLLP_VUINT32_T MMC_RESERVED2[12]; /* reserved for different fifo */
XLLP_VUINT32_T SD_RXFIFO; /* receive fifo for 1,2,3 or 4 bytes */
XLLP_VUINT32_T SD_TXFIFO; /* transmit fifo for 1,2,3 or 4 bytes */
} XLLP_MMC_T, *P_XLLP_MMC_T;
/* mmc start and stop clock register */
#define XLLP_STRPCL_STPCLK XLLP_BIT_0; // stop clock; writing 1 stops the MMC clock
#define XLLP_STRPCL_STRTCLK XLLP_BIT_1; // start clock; writing 1 starts the MMC clock
// bit automatically cleared to 0
// MMC status register
#define XLLP_STAT_TORD XLLP_BIT_0 // read timed out
#define XLLP_STAT_TORSPNS XLLP_BIT_1 // card response timed out
#define XLLP_STAT_CRCWRERR XLLP_BIT_2 // card observed erroneous transmission of data
#define XLLP_STAT_CRCRDERR XLLP_BIT_3 // crc error on recieved data
#define XLLP_STAT_DATAERRTKN XLLP_BIT_4 // spi data error token has been received
#define XLLP_STAT_RESCRCERR XLLP_BIT_5 // response crc error
#define XLLP_STAT_CLKEN XLLP_BIT_8 //MMC clock is on
#define XLLP_STAT_FLASHERR XLLP_BIT_9 //MMC clock is on
#define XLLP_STAT_DATATRANDONE XLLP_BIT_11 // data transmission card has completed
#define XLLP_STAT_PRGDONE XLLP_BIT_12 // card has finished programming and is not busy
#define XLLP_STAT_ENDCMDRES XLLP_BIT_13 // command and response sequence has completed
// MMC Clock rate register
#define XLLP_CLKRT 0x7
typedef enum
{
XLLP_MMC_20MHz = 0x0,
XLLP_MMC_10MHz = 0x1,
XLLP_MMC_5MHz = 0x2,
XLLP_MMC_2_5MHz = 0x3,
XLLP_MMC_1_25MHz = 0x4,
XLLP_MMC_625MHz = 0x5,
XLLP_MMC_3125MHz = 0x6
}XLLP_MMC_CLKRATE;
// MMC SPI register
#define XLLP_MMC_SPI_MODE XLLP_BIT_0 // enables spi mode
#define XLLP_MMC_SPI_CRCON XLLP_BIT_1 // enable crc generation and verification
#define XLLP_MMC_SPI_CSEN XLLP_BIT_2 // enables spi chip select
#define XLLP_MMC_SPI_CSADDR XLLP_BIT_3 // 1 enables CS1 0 enable CS0
// MMC command data register
#define XLLP_MMC_CMDAT_RESTYPE 0x3
typedef enum
{
XLLP_MMC_NORESPONSE = 0x0,
XLLP_MMC_MMCSPIR1 = 0x1,
XLLP_MMC_MMCSPIR2 = 0x2,
XLLP_MMC_MMCR3 = 0x3
}XLLP_MMC_RESPFRMT;
#define XLLP_MMC_CMDAT_DATAEN XLLP_BIT_2 // current command includes data
#define XLLP_MMC_CMDAT_WRRD XLLP_BIT_3 // 0 specifies a read 1 specifies a write
#define XLLP_MMC_CMDAT_STRMBLK XLLP_BIT_4 //current command is in stream block mode
#define XLLP_MMC_CMDAT_BUSY XLLP_BIT_5 // specifies whether a busy signal is expected after
// after current command for no data trans. only
#define XLLP_MMC_CMDAT_INIT XLLP_BIT_6 // precede command sequence with 80 clocks
#define XLLP_MMC_CMDAT_DMAEN XLLP_BIT_7 // DMA mode
//these are also part of the CMDAT reg but specificly only if MMC_SD_CMDAT register is used
#define XLLP_MMC_CMDAT_SD4DAT XLLP_BIT_8 // (1)enable 4 bit data transfer; only valid for SD
#define XLLP_MMC_CMDAT_SDPROT XLLP_BIT_9 // SD protocol (1) vs. MMC protocol(0)
// MMC Resto register
#define XLLP_MMC_RESTOBITS 0x7f
// MMC read time out register
#define XLLP_MMC_RDTOBITS 0xffff
// MMC block length register
#define XLLP_MMC_BLKLENBITS 0x3ff
// MMC number of blocks register
#define XLLP_MMC_NUMBLKBITS 0xffff
// MMC partial full buffer register
#define XLLP_MMC_PRTBUF XLLP_BIT_0 // buffer is partially full and must be swapped to the other transmit buffer
// MMC interrupt mask register
#define XLLP_MMC_I_MASK_DATATRANSDONE XLLP_BIT_0 // data transfer is done
#define XLLP_MMC_I_MASK_PRGDONE XLLP_BIT_1 // programming is done
#define XLLP_MMC_I_MASK_ENDCMDRES XLLP_BIT_2 // end command response
#define XLLP_MMC_I_MASK_STOPCMD XLLP_BIT_3 // ready for stop transaction command
#define XLLP_MMC_I_MASK_CLKISOFF XLLP_BIT_4 // clock is off
#define XLLP_MMC_I_MASK_RXFIFORDREQ XLLP_BIT_5 //receive fifo read request
#define XLLP_MMC_I_MASK_TXFIFOWRREQ XLLP_BIT_6 // transmit fifo write request
#define XLLP_MMC_I_MASK_TINT XLLP_BIT_7 // transmit fifo write request
// MMC current interrupt register
#define XLLP_MMC_I_REG_DATATRANSDONE XLLP_BIT_0 // data transfer is done cleared by the mmc_stat[dataDone]
#define XLLP_MMC_I_REG_PRGDONE XLLP_BIT_1 // programming is done cleared by the mmc_stat[prgDone]
#define XLLP_MMC_I_REG_ENDCMDRES XLLP_BIT_2 // end command response cleared by the mmc_stat[endCmdRes]
#define XLLP_MMC_I_REG_STOPCMD XLLP_BIT_3 // ready for stop transaction command cleared when cmd12 is loaded
#define XLLP_MMC_I_REG_CLKISOFF XLLP_BIT_4 // clock is off cleared by the mmc_stat[clkEn]
#define XLLP_MMC_I_REG_RXFIFORDREQ XLLP_BIT_5 //receive fifo read request cleared after each read but immediately
// set again unless the fifo is empty
#define XLLP_MMC_I_REG_TXFIFOWRREQ XLLP_BIT_6 // transmit fifo write request cleared after each write but immediately
// set again unless the fifo is empty
#define XLLP_MMC_I_REG_TINT XLLP_BIT_7 // transmit fifo write request
// MMC Command registers that specifies the commands
#define XLLP_MMC_CMDBITS 0x3f
typedef enum
{
XLLP_MMC_SPICMD0 = 0x0, // go idle state
XLLP_MMC_SPICMD1 = 0x1, // send op command
XLLP_MMC_CMD2 = 0x2, // all send cid
XLLP_MMC_CMD3 = 0x3, // set relative addr
XLLP_MMC_CMD4 = 0x4, // set dsr
XLLP_MMC_CMD7 = 0x7, // select/deselect card
XLLP_MMC_SPICMD9 = 0x9, // send csd
XLLP_MMC_SPICMD10 = 0xa, // send cid
XLLP_MMC_CMD11 = 0xb, // read data until stop
XLLP_MMC_CMD12 = 0xc, // stop transmission
XLLP_MMC_SPICMD13 = 0xd, // send status
XLLP_MMC_CMD15 = 0xf, // go inactive state
XLLP_MMC_SPICMD16 = 0x10, // set block length
XLLP_MMC_SPICMD17 = 0x11, // read single block
XLLP_MMC_CMD18 = 0x12, // read multiple block
XLLP_MMC_CMD20 = 0x14, // write data until stop
XLLP_MMC_SPICMD24 = 0x18, // write block
XLLP_MMC_CMD25 = 0x19, // write multiple block
XLLP_MMC_CMD26 = 0x1a, // program CID
XLLP_MMC_SPICMD27 = 0x1b, // program CSD
XLLP_MMC_SPICMD28 = 0x1c, // set write prot
XLLP_MMC_SPICMD29 = 0x1d, // clr write prot
XLLP_MMC_SPICMD30 = 0x1e, // send write prot
XLLP_MMC_SPICMD32 = 0x200, // tag sector start
XLLP_MMC_SPICMD33 = 0x201, // tag sector end
XLLP_MMC_SPICMD34 = 0x202, // untag sector
XLLP_MMC_SPICMD35 = 0x203, // tag erase group start
XLLP_MMC_SPICMD36 = 0x204, // tag erase group end
XLLP_MMC_SPICMD37 = 0x205, // untag erase group
XLLP_MMC_SPICMD38 = 0x206, // erase
XLLP_MMC_CMD39 = 0x207, //fast IO
XLLP_MMC_CMD40 = 0x208, // go irq state
XLLP_MMC_SPICMD42 = 0x2a, // lock-unlock
XLLP_MMC_SPICMD55 = 0x37, // app cmd
XLLP_MMC_SPICMD56 = 0x38, // gen cmd
XLLP_SPI_CMD58 = 0x3a, // read ocr
XLLP_SPI_CMD59 = 0x3b, // crc on-off
XLLP_MMC_CMD60 = 0x3c, // reserved for manufacturer
XLLP_MMC_CMD61 = 0x3d, // reserved for manufacturer
XLLP_MMC_CMD62 = 0x3e, // reserved for manufacturer
XLLP_MMC_CMD63 = 0x3f // reserved for manufacturer
} XLLP_MMC_CMD;
// MMC upper 16 bits of the argument for the current command
#define XLLP_MMC_ARGHBITS 0xffff
// MMC lower 16 bits of the argument for the current command
#define XLLP_MMC_ARGLBITS 0xffff << 16
// MMC response fifo
#define XLLP_MMC_RESFIFOBITS 0xffff
// MMC Receive fifo
#define XLLP_MMC_RXFIFO1BYTE 0xff
#define XLLP_MMC_RXFIFO2BYTE 0xffff
#define XLLP_MMC_RXFIFO3BYTE 0xffffff
#define XLLP_MMC_RXFIFO4BYTE 0xffffffff
// MMC transmit fifo
#define XLLP_MMC_TXFIFO1BYTE 0xff
#define XLLP_MMC_TXFIFO2BYTE 0xffff
#define XLLP_MMC_TXFIFO3BYTE 0xffffff
#define XLLP_MMC_TXFIFO4BYTE 0xffffffff
// function prototypes
void XllpMmcSdHWInit(XLLP_UINT32_T , XLLP_UINT32_T );
void XllpMmcSetUpClock(P_XLLP_MMC_T mmcRegs, XLLP_MMC_CLKRATE rate, XLLP_BOOL_T strClck);
void XllpMmcXtractResp(P_XLLP_MMC_T mmcRegs, P_XLLP_UINT16_T buff, XLLP_MMC_RESPFRMT response);
XLLP_BOOL_T XllpMmcSetupCmd(P_XLLP_MMC_T mmcRegs, XLLP_MMC_CMD cmd,
XLLP_INT32_T arg, XLLP_INT32_T To);
void XllpSdSetupCmd(P_XLLP_MMC_T mmcRegs, XLLP_MMC_CMD cmd,
XLLP_INT32_T arg, XLLP_INT32_T To);
void XllpMmcSdSetupXCmd(P_XLLP_MMC_T mmcRegs, XLLP_INT32_T FlSz,
XLLP_INT32_T BlkSz);
void XllpMmcSdInts(P_XLLP_MMC_T mmcRegs, XLLP_INT8_T SetMask);
// in here strictly for functionality
typedef struct
{
XLLP_VUINT32_T GPLR0; /* Level Detect Reg. Bank 0 */
XLLP_VUINT32_T GPLR1; /* Level Detect Reg. Bank 1 */
XLLP_VUINT32_T GPLR2; /* Level Detect Reg. Bank 2 */
XLLP_UINT32_T GPDR0; /* Data Direction Reg. Bank 0 */
XLLP_UINT32_T GPDR1; /* Data Direction Reg. Bank 1 */
XLLP_UINT32_T GPDR2; /* Data Direction Reg. Bank 2 */
XLLP_UINT32_T GPSR0; /* Pin Output Set Reg. Bank 0 */
XLLP_UINT32_T GPSR1; /* Pin Output Set Reg. Bank 1 */
XLLP_UINT32_T GPSR2; /* Pin Output Set Reg. Bank 2 */
XLLP_UINT32_T GPCR0; /* Pin Output Clr Reg. Bank 0 */
XLLP_UINT32_T GPCR1; /* Pin Output Clr Reg. Bank 1 */
XLLP_UINT32_T GPCR2; /* Pin Output Clr Reg. Bank 2 */
XLLP_UINT32_T GRER0; /* Ris. Edge Detect Enable Reg. Bank 0 */
XLLP_UINT32_T GRER1; /* Ris. Edge Detect Enable Reg. Bank 1 */
XLLP_UINT32_T GRER2; /* Ris. Edge Detect Enable Reg. Bank 2 */
XLLP_UINT32_T GFER0; /* Fal. Edge Detect Enable Reg. Bank 0 */
XLLP_UINT32_T GFER1; /* Fal. Edge Detect Enable Reg. Bank 1 */
XLLP_UINT32_T GFER2; /* Fal. Edge Detect Enable Reg. Bank 2 */
XLLP_VUINT32_T GEDR0; /* Edge Detect Status Reg. Bank 0 */
XLLP_VUINT32_T GEDR1; /* Edge Detect Status Reg. Bank 1 */
XLLP_VUINT32_T GEDR2; /* Edge Detect Status Reg. Bank 2 */
XLLP_UINT32_T GAFR0_L; /* Alt. Function Select Reg.[ 0:15 ] */
XLLP_UINT32_T GAFR0_U; /* Alt. Function Select Reg.[ 16:31 ] */
XLLP_UINT32_T GAFR1_L; /* Alt. Function Select Reg.[ 32:47 ] */
XLLP_UINT32_T GAFR1_U; /* Alt. Function Select Reg.[ 48:63 ] */
XLLP_UINT32_T GAFR2_L; /* Alt. Function Select Reg.[ 64:79 ] */
XLLP_UINT32_T GAFR2_U; /* Alt. Function Select Reg.[ 80:95 ] */
XLLP_UINT32_T GAFR3_L; /* Alt. Function Select Reg.[ 96:111] */
XLLP_UINT32_T GAFR3_U; /* Alt. Function Select Reg.[112:120] */
XLLP_UINT32_T RESERVED1[125]; /* addr. offset 0x074-0x0fc */
XLLP_VUINT32_T GPLR3; /* Level Detect Reg. Bank 3 */
XLLP_UINT32_T RESERVED2[2]; /* addr. offset 0x104-0x108 */
XLLP_UINT32_T GPDR3; /* Data Direction Reg. Bank 3 */
XLLP_UINT32_T RESERVED3[2]; /* addr. offset 0x110-0x114 */
XLLP_UINT32_T GPSR3; /* Pin Output Set Reg. Bank 3 */
XLLP_UINT32_T RESERVED4[2]; /* addr. offset 0x11c-0x120 */
XLLP_UINT32_T GPCR3; /* Pin Output Clr Reg. Bank 3 */
XLLP_UINT32_T RESERVED5[2]; /* addr. offset 0x128-0x12c */
XLLP_UINT32_T GRER3; /* Ris. Edge Detect Enable Reg. Bank 3 */
XLLP_UINT32_T RESERVED6[2]; /* addr. offset 0x134-0x138 */
XLLP_UINT32_T GFER3; /* Fal. Edge Detect Enable Reg. Bank 3 */
XLLP_UINT32_T RESERVED7[2]; /* addr. offset 0x140-0x144 */
XLLP_VUINT32_T GEDR3; /* Edge Detect Status Reg. Bank 3 */
} XLLP_GPIO_T, *P_XLLP_GPIO_T;
typedef struct
{
XLLP_VUINT32_T CCCR; /* core clock configuration register */
XLLP_VUINT32_T CKEN; /* clock-enable register */
XLLP_VUINT32_T OSCC; /* oscillator configuration register */
XLLP_VUINT32_T CCSR; /* Core clock status register */
} XLLP_CLOCK_T, *P_XLLP_CLOCK_T;
#endif // end of .h file
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