lcd.asm

来自「ST7 Software LCD driver」· 汇编 代码 · 共 250 行

st7/

;************************************************************************ 
; TITLE:                LCD.ASM
; AUTHOR:               Microcontroller Application Team
; DESCRIPTION:          Software driver for a 4 backplane LCD display.
;                       Use only one timer to generate the appropriate lcd timing
; Version:		Ver 1.0                   
;************************************************************************


        TITLE    "LCD.ASM"           
        
        MOTOROLA
        .NOLIST
        #INCLUDE "ST72321.inc"		; include ST72321 registers and memory mapping file
        #INCLUDE "variable.inc"		; include general variable file
        .LIST
        
;************************************************************************
                                        
         
;***********************************************************************
;       Variables, constants defined and referenced locally
;       You can define your own values for a local reference here
;***********************************************************************

;************************************************************************
;       Public routines   (defined here)
;************************************************************************
; routines
                
; We could have used a dot in front of the label's name to declare the routine 
; as visible by others modules in the project.

      
;************************************************************************
;       Extern routines   (defined elsewhere)
;
;       The EXTERN directive will be seen by the linker as a call
;       instruction to another routine written in another file
;************************************************************************
; routines

;**********************************************************
;       Program code
;**********************************************************

        WORDS               ; define subsequent addresses as words
                            ; meaning that all instructions are located 
                            ; in the address field after 0FFh in the ST72251
                            ; memory mapping

    segment 'rom'
.COM1		BYTE	$01
.COM2		BYTE	$02
.COM3		BYTE	$04
.COM4		BYTE	$08

.CPL0COM1	BYTE	$FE
.CPL0COM2	BYTE	$FD
.CPL0COM3	BYTE	$FB
.CPL0COM4	BYTE	$F7

;*****************************************************************
; TimerA driver - TimerA used for LCD timing generation: 
; - PC[0..3] dedicated to COM[1..4] respectively. They provide 3 levels thanks to 2 external pull up 
;   and pull down resistors for each pin, and the open drain output feature: 0, Vdd/2, and Vdd
; - For segment signals which are normal numerical signal (0 or 1) PA[0..5], PB[0..7], PD[0..7],PF[0..7],PE[6..7]are used
;	 as output push-pull mode 
; - The lcd timing is divided in 4 parts & each part has oc1_1, oc2, oc1_2, oc2 events
; - 4 interrupts are generated per control period(4msec)& 16 per frame period(16msec)
;*****************************************************************

.tima_rt    ; timer status register is read before entering into ISR
            BTJT TASR,#6,oc1  ; Check if Output Compare1 interrupt
            BTJT TASR,#3,oc2  ; Check if Output Compare2 interrupt
            JRT out            
oc2	    LD A,TAOC2LR    ; access OC2LR to clear the OCF2 flag
            CLR TACLR      ; reset timer counter by any write to the LSB
            LD A,#$00      ; Deactivate all COM & SEG lines 
            LD PBDR,A
            LD PDDR,A
            LD PFDR,A
            LD A,PEDR      
            AND A,#$3f     ; Deactivate PE6-PE7
            LD PEDR,A 
            LD A,PADR      ; Deactivate PA0-PA5
            AND A,#$c0
            LD PADR,A
                        
            LD A,PCOR
            OR A,#$0f 
            LD PCOR,A
            
            LD A,PCDR
            AND A,#$F0      
            LD PCDR,A
            JRT out
            
oc1_1           		
	   inc var
	   LD X,lcdcr     ; lcdcr saves the index no(0-3) for each control period 
	   LD A,PADR
	   AND A,#$c0
	   OR A,(segA1,X) ; segments which are to be turned ON, are loaded with value 1, otherwise 0  
           LD PADR,A       
           LD A,(segB1,X) ; segments which are to be turned ON, are loaded with value 1, otherwise 0  
           LD PBDR,A        
           LD A,(segD1,X) ; segments which are to be turned ON, are loaded with value 1, otherwise 0  
           LD PDDR,A  
           LD A,(segF1,X) ; segments which are to be turned ON, are loaded with value 1, otherwise 0  
           LD PFDR,A
           LD A,PEDR
           AND A,#$3f  
	   OR A,(segE1,X) ; segments which are to be turned ON, are loaded with value 1, otherwise 0  
           LD PEDR,A  

  
	   LD A,(COM1,X)       
	   LD PCOR,A
	   	   
	   LD A,(CPL0COM1,X)	
	   LD PCDR,A	  
out        IRET
                

oc1	    LD A,TAOC1LR    ; Read OC1LR register to clear the OCF1 flag
            LD A,var
            TNZ A
            JREQ oc1_1



oc1_2       CLR var
            LD X,lcdcr     ; lcdcr saves the index no(0-3) for each control period 
	    
	    LD A,PADR
	    AND A,#$c0
	    OR A,(segA1,X) ; segments are loaded with values which are inverted rto the value set during the oc1_1 
            CPL A
            LD PADR,A       
            LD A,(segB1,X) ; segments are loaded with values which are inverted rto the value set during the oc1_1 
            CPL A 
            LD PBDR,A        
            LD A,(segD1,X) ; segments are loaded with values which are inverted rto the value set during the oc1_1
            CPL A   
            LD PDDR,A  
            LD A,(segF1,X) ; segments are loaded with values which are inverted rto the value set during the oc1_1
            CPL A   
            LD PFDR,A  
	    LD A,PEDR
	    AND A,#$3f
	    OR A,(segE1,X) ; segments are loaded with values which are inverted rto the value set during the oc1_1
            CPL A   
            LD PEDR,A  
		    
	    
    
	    LD A,(COM1,X)  ; COM corresponding to the control period(X 0-3)which was set to 0 during oc1_1 will become 0 & others Vlcd/2     
	    LD PCOR,A
	   	   
	    LD A,#$ff	
	    LD PCDR,A
	    	    	   	    
	    LD A,lcdcr     ; increment LCDDR and reset when equal to 4
	    ADD A,#1       
	    CP A,#4
	    JRNE oc2_out
	    CLR A
oc2_out	    LD lcdcr,A
	    JRT out

                
;*****************************************************************
; TimerA initialisation  
; (Output Compare1 Period) + (Output Compare2 Period) = 2msec. 
; (Refer figure8 in AN1048)
; Total Frame Period- 16msec 
; Frame Frequency- 62.5Hz
;*****************************************************************
.timer_config
            
            CLR A
            LD lcdcr,A              ; initialize lcd software control register
            LD var,A
            LD A,#$03               
            LD TAOC1HR,A            ; output compare 1 IT when the counter reaches 0370h 
            LD A,#$70               ; Values are set according to Fcpu= 8Mhz
            LD TAOC1LR,A             
            LD A,#$07               
            LD TAOC2HR,A            ; ouput compare 2 IT when the counter reaches 07ceh  
            LD A,#$ce               ; Values are set according to Fcpu= 8Mhz
            LD TAOC2LR,A
            LD A,#$40
            LD TACR1,A              ; Timer output compare interrupt enabled
            LD A,#$08
            LD TACR2,A              ; Timer counter clock is CPU clk/8
            RET
                  
                   
;*****************************************************************
; Ports initialisation for LCD pins
;*****************************************************************

                                        ; CAUTION!! has to be runned just before lcd program
                                        ; is runned, because lcd pins must never be connected
                                        ; to steady levels. As long as lcd is not used, let
                                        ; the ST7 pins in reset state (input) so that the lcd
                                        ; is not supplied. You can configure them in an other
                                        ; state exept in ouput push pull!
.port_init
             LD A,#$ff                 
             LD PBDDR,A              ; PORT A0-A5, B0-B7, D0-D7, F0-F7, E6-E7 will be dedicated to the segments outputs
             LD PDDDR,A
	     LD PFDDR,A
	     LD A,#$3f
	     LD PADDR,A
	     LD A,#$c0 
	     LD PEDDR,A  
	   			                
	     LD A,#$ff               
	     LD PBOR,A               ; Configure the PORT A0-A5, B0-B7, D0-D7, F0-F7, E6-E7 in O/P push pull   
             LD PDOR,A               
             LD PFOR,A
             LD A,#$3f
             LD PAOR,A
             LD A,#$c0 
	     LD PEOR,A 
             
                  
             LD A,#$00
             LD PADR,A
             LD PBDR,A
             LD PDDR,A
             LD PFDR,A 
             LD PEDR,A
                                 

             LD A,#$0F               ; configure PC[0..3] as output open drain             
             LD PCDDR,A
             clr PCOR                ; they will be dedicated to the backplanes outputs
             LD PCDR,A

             ret
             END