st72321.asm

ST7 Software LCD driver

st7/

;**************** STMicroelectronics **********************
;
; PROJECT  :         Software LCD Driver
; COMPILER :         ST7 ASSEMBLY CHAIN
;
;
; TITLE:             ST72321.ASM
; DESCRIPTION:       ST72321 Register and memory mapping 
;************************************************************************

    

    BYTES           ; following addresses are 8 bit length

;********************************************************************
    segment byte at 0-7F 'periph'
;********************************************************************

;**********************************************************************
;                        I/O Ports registers
;**********************************************************************
                
.PADR   DS.B    1       ; port A data register
.PADDR  DS.B    1       ; port A data direction register
.PAOR   DS.B    1       ; port A option register
    
.PBDR   DS.B    1       ; port B data register
.PBDDR  DS.B    1       ; port B data direction register
.PBOR   DS.B    1       ; port B option register

.PCDR   DS.B    1       ; port C data register
.PCDDR  DS.B    1       ; port C data direction register
.PCOR   DS.B    1       ; port C option register

.PDDR   DS.B    1       ; port D data register
.PDDDR  DS.B    1       ; port D data direction register  
.PDOR   DS.B    1       ; port D option register                  

.PEDR   DS.B    1       ; port E data register
.PEDDR  DS.B    1       ; port E data direction register 
.PEOR   DS.B    1       ; portE option register       
                
.PFDR   DS.B    1       ; port F data register
.PFDDR  DS.B    1       ; port F data direction register         
.PFOR   DS.B    1       ; port F option register
                
reserved0 DS.B  6       ; unused

          DS.B	20      ; not used in the application
.MCCSR    DS.B  1
.MCCBCR   DS.B  1
reserved1 DS.B  3       ; unused


;**********************************************************************
;                        timer A registers
;**********************************************************************
    
.TACR2   DS.B    1       ; timer A control register 2
.TACR1   DS.B    1       ; timer A control register 1
.TASR    DS.B    1       ; timer status register
.TAIC1HR DS.B    1       ; timer A input capture 1 high register 
.TAIC1LR DS.B    1       ; timer A input capture 1 low register
.TAOC1HR DS.B    1       ; timer A output compare 1 high register
.TAOC1LR DS.B    1       ; timer A output compare 1 low register
.TACHR   DS.B    1       ; timer A counter high register
.TACLR   DS.B    1       ; timer A counter low register
.TAACHR  DS.B    1       ; timer A alternate counter high register
.TAACLR  DS.B    1       ; timer A alternate counter low register
.TAIC2HR DS.B    1       ; timer A input capture 2 high register 
.TAIC2LR DS.B    1       ; timer A input capture 2 low register
.TAOC2HR DS.B    1       ; timer A output compare 2 high register
.TAOC2LR DS.B    1       ; timer A output compare 2 low register
 
reserved4 DS.B   1       ; unused

;**********************************************************************
;                        timer B registers
;**********************************************************************

.TBCR2   DS.B    1       ; timer B control register 2
.TBCR1   DS.B    1       ; timer B control register 1
.TBSR    DS.B    1       ; timer B status register
.TBIC1HR DS.B    1       ; timer B input capture 1 high register 
.TBIC1LR DS.B    1       ; timer B input capture 1 low register
.TBOC1HR DS.B    1       ; timer B output compare 1 high register
.TBOC1LR DS.B    1       ; timer B output compare 1 low register
.TBCHR   DS.B    1       ; timer B counter high register
.TBCLR   DS.B    1       ; timer B counter low register
.TBACHR  DS.B    1       ; timer B alternate counter high register
.TBACLR  DS.B    1       ; timer B alternate counter low register
.TBIC2HR DS.B    1       ; timer B input capture 2 high register 
.TBIC2LR DS.B    1       ; timer B input capture 2 low register
.TBOC2HR DS.B    1       ; timer B output compare 2 high register
.TBOC2LR DS.B    1       ; timer B output compare 2 low register
         DS.B    8    
reserved5 DS.B  24      ; unused

;**********************************************************************
;                       ADC registers
;**********************************************************************

.ADCCSR  DS.B    1       ; adc control status register
.ADCDRH  DS.B    1       ; adc data register  
.ADCDRL  DS.B    1       ; adc data register

;**********************************************************************
    segment byte at 80-FF 'ram0' ;Zero Page
;**********************************************************************


    WORDS           ; following addresses are 16 bit length


;**********************************************************************
;   for ST72311J2 or ST72311N2 with 8K ROM & 256 byte RAM

    segment byte at 100-17F     'stack'
    segment byte at E000-FFDF   'rom' ;  
      
;**********************************************************************    
;   for ST72311J4 or ST72311N4 with 16K ROM & 512 byte RAM
     
;     segment byte at 100-1FF    'stack'
;     segment byte at 200-27F    'ram1'
;    segment byte at C000-FFDF  'rom'
  

;**********************************************************************
    segment byte at FFE0-FFFF 'vectit'
;**********************************************************************

        end