lcd.lst

ST7 Software LCD driver

 111  E0F5   B709                          LD       PDDR,A  
 112  E0F7   E690                          LD       A,(segF1,X)   ; segments which are to be 
                                                                  ;turned ON, are loaded with 
                                                                  ;value 1, otherwise 0  
 113  E0F9   B70F                          LD       PFDR,A
 114  E0FB   B60C                          LD       A,PEDR
 115  E0FD   A43F                          AND      A,#$3f  
 116  E0FF   EA94                          OR       A,(segE1,X)   ; segments which are to be 
                                                                  ;turned ON, are loaded with 
                                                                  ;value 1, otherwise 0  
 117  E101   B70C                          LD       PEDR,A  
 118                             
 119                                       
 120  E103   D6E0AD                        LD       A,(COM1,X)       
 121  E106   B708                          LD       PCOR,A
 122                                       
 123  E108   D6E0B1                        LD       A,(CPL0COM1,X)  
 124  E10B   B706                          LD       PCDR,A        
 125  E10D   80                  out       IRET     
 126                                       
 127                             
 128  E10E   B637                oc1       LD       A,TAOC1LR      ; Read OC1LR register to clear 
                                                                  ;the OCF1 flag
 129  E110   B698                          LD       A,var
 130  E112   4D                            TNZ      A
 131  E113   27CE                          JREQ     oc1_1
 132                             
METAi Assembler  6.02  (C)1987-91 Crash Barrier  Tue Jan 20 19:34:04 2004
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                                               D:\usr\jatin\AN\Code\LCD_SW\LCD_SW\LCD_4COM\lcd.asm

 133                             
 134                             
 135  E115   3F98                oc1_2     CLR      var
 136  E117   BE83                          LD       X,lcdcr       ; lcdcr saves the index no(0-3) 
                                                                  ;for each control period 
 137                                       
 138  E119   B600                          LD       A,PADR
 139  E11B   A4C0                          AND      A,#$c0
 140  E11D   EA84                          OR       A,(segA1,X)   ; segments are loaded with 
                                                                  ;values which are inverted rto 
                                                                  ;the value set during the oc1_1 
                                                                  ;
 141  E11F   43                            CPL      A
 142  E120   B700                          LD       PADR,A       
 143  E122   E688                          LD       A,(segB1,X)   ; segments are loaded with 
                                                                  ;values which are inverted rto 
                                                                  ;the value set during the oc1_1 
                                                                  ;
 144  E124   43                            CPL      A 
 145  E125   B703                          LD       PBDR,A        
 146  E127   E68C                          LD       A,(segD1,X)   ; segments are loaded with 
                                                                  ;values which are inverted rto 
                                                                  ;the value set during the oc1_1
 147  E129   43                            CPL      A   
 148  E12A   B709                          LD       PDDR,A  
 149  E12C   E690                          LD       A,(segF1,X)   ; segments are loaded with 
                                                                  ;values which are inverted rto 
                                                                  ;the value set during the oc1_1
 150  E12E   43                            CPL      A   
 151  E12F   B70F                          LD       PFDR,A  
 152  E131   B60C                          LD       A,PEDR
 153  E133   A43F                          AND      A,#$3f
 154  E135   EA94                          OR       A,(segE1,X)   ; segments are loaded with 
                                                                  ;values which are inverted rto 
                                                                  ;the value set during the oc1_1
 155  E137   43                            CPL      A   
 156  E138   B70C                          LD       PEDR,A  
 157                                       
 158                                       
 159                                       
 160  E13A   D6E0AD                        LD       A,(COM1,X)    ; COM corresponding to the 
                                                                  ;control period(X 0-3)which was 
                                                                  ;set to 0 during oc1_1 will 
                                                                  ;become 0 & others Vlcd/2     
 161  E13D   B708                          LD       PCOR,A
 162                                       
 163  E13F   A6FF                          LD       A,#$ff        
 164  E141   B706                          LD       PCDR,A
 165                                       
 166  E143   B683                          LD       A,lcdcr       ; increment LCDDR and reset when
                                                                  ; equal to 4
 167  E145   AB01                          ADD      A,#1       
 168  E147   A104                          CP       A,#4
 169  E149   2601                          JRNE     oc2_out
 170  E14B   4F                            CLR      A
 171  E14C   B783                oc2_out   LD       lcdcr,A
 172  E14E   20BD                          JRT      out
METAi Assembler  6.02  (C)1987-91 Crash Barrier  Tue Jan 20 19:34:04 2004
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                                               D:\usr\jatin\AN\Code\LCD_SW\LCD_SW\LCD_4COM\lcd.asm

 173                             
 174                                       
 175                             ;*************************************************************
                                 ;****
 176                             ; TimerA initialisation  
 177                             ; (Output Compare1 Period) + (Output Compare2 Period) = 2msec.
                                 ; 
 178                             ; (Refer figure8 in AN1048)
 179                             ; Total Frame Period- 16msec 
 180                             ; Frame Frequency- 62.5Hz
 181                             ;*************************************************************
                                 ;****
 182                             .timer_config  
 183                                       
 184  E150   4F                            CLR      A
 185  E151   B783                          LD       lcdcr,A                ; initialize lcd software 
                                                                  ;control register
 186  E153   B798                          LD       var,A
 187  E155   A603                          LD       A,#$03               
 188  E157   B736                          LD       TAOC1HR,A              ; output compare 1 IT when the 
                                                                  ;counter reaches 0370h 
 189  E159   A670                          LD       A,#$70                 ; Values are set according to 
                                                                  ;Fcpu= 8Mhz
 190  E15B   B737                          LD       TAOC1LR,A             
 191  E15D   A607                          LD       A,#$07               
 192  E15F   B73E                          LD       TAOC2HR,A              ; ouput compare 2 IT when the 
                                                                  ;counter reaches 07ceh  
 193  E161   A6CE                          LD       A,#$ce                 ; Values are set according to 
                                                                  ;Fcpu= 8Mhz
 194  E163   B73F                          LD       TAOC2LR,A
 195  E165   A640                          LD       A,#$40
 196  E167   B732                          LD       TACR1,A                ; Timer output compare interrupt
                                                                  ; enabled
 197  E169   A608                          LD       A,#$08
 198  E16B   B731                          LD       TACR2,A                ; Timer counter clock is CPU 
                                                                  ;clk/8
 199  E16D   81                            RET      
 200                                       
 201                                       
 202                             ;*************************************************************
                                 ;****
 203                             ; Ports initialisation for LCD pins
 204                             ;*************************************************************
                                 ;****
 205                             
 206                                                              ; CAUTION!! has to be runned 
                                                                  ;just before lcd program
 207                                                              ; is runned, because lcd pins 
                                                                  ;must never be connected
 208                                                              ; to steady levels. As long as 
                                                                  ;lcd is not used, let
 209                                                              ; the ST7 pins in reset state 
                                                                  ;(input) so that the lcd
 210                                                              ; is not supplied. You can 
                                                                  ;configure them in an other
 211                                                              ; state exept in ouput push 
                                                                  ;pull!
METAi Assembler  6.02  (C)1987-91 Crash Barrier  Tue Jan 20 19:34:04 2004
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                                               D:\usr\jatin\AN\Code\LCD_SW\LCD_SW\LCD_4COM\lcd.asm

 212                             .port_init  
 213  E16E   A6FF                          LD       A,#$ff                 
 214  E170   B704                          LD       PBDDR,A                ; PORT A0-A5, B0-B7, D0-D7, 
                                                                  ;F0-F7, E6-E7 will be dedicated 
                                                                  ;to the segments outputs