spi.asm

SPI COMMUNICATION BETWEEN ST7 AND EEPROM

;|										|
;|INTERNAL PARAMETERS:								|
;| A (accumulator)								|
;|										|
;|OUTPUT PARAMETERS:								|
;| None										|
;+------------------------------------------------------------------------------+     
.byte_write_l

	bres	PBDR,#DEV_P       	; Tie to low E2PROM S pin 
         
      					; Send write in lower page instruction 
        ld    	Y,#$02
        ld    	SPIDR,Y           	; Value sent when put into the SPIDR
wait4   btjf  	SPICSR,#7,wait4    	; Wait for SPIF bit to go up (data sent) 
        ld    	Y,SPIDR           	; Second step to clear the SPIF bit       

      					; Send write memory address
        ld	SPIDR,A           	; Write at address A (16 bytes) 
wait5   btjf	SPICSR,#7,wait5    	; Wait for SPIF bit to go up (data sent)
        ld	Y,SPIDR           	; Second step to clear the SPIF bit       
      
      	add	A,#$10
      	ld	temp1,A                 ; 16 bytes written at a time
      	sub	A,#$10
              
write_again      			; Write data 
        ld    	SPIDR,X           	; Data = X 
wait6   btjf  	SPICSR,#7,wait6    	; Wait for SPIF bit to go up (data sent) 
        ld    	Y,SPIDR          	; Second step to clear the SPIF bit       
                                        
        				; End of writing sequence? 
        inc   	X                 	; Increment X  
        CP	X,temp1                 ; 16 bytes written at a time
        jrult 	write_again        	; If not, still write, else end
                                                                             	                        
      					; Deselect device 
        bset	PBDR,#DEV_P       	; Low to high transition on the S pin for
        				; the latch 
        ret 
;********************************************************************************

              
;********************************************************************************
;+------------------------------------------------------------------------------+
;|										|
;|			READ ROUTINE						|
;|										|
;+------------------------------------------------------------------------------+
;|ROUTINE DESCRIPTION:								|
;| This routine enables to read data value at memory address in lower page	|
;|										|
;|INPUT PARAMETERS:								|
;| Device pin (here 3 for PB3), memory address					|
;|										|
;|INTERNAL PARAMETERS:								|
;| A (accumulator)								|
;|										|
;|OUTPUT PARAMETERS:								|
;| Data value									|
;+------------------------------------------------------------------------------+     
.byte_read_l
        bres	PBDR,#DEV_P       	; Tie to low E2PROM S pin 
       
      					; Send read instruction
        ld    	Y,#$03 
        ld    	SPIDR,Y           	; Value sent when put into the SPIDR 
wait9   btjf  	SPICSR,#7,wait9    	; Wait for SPIF bit to go up (data sent) 
        ld    	Y,SPIDR          	; Second step to clear the SPIF bit       

					; Send read memory address 
        ld    	SPIDR,A           	; Read at address A 
wait10  btjf  	SPICSR,#7,wait10   	; Wait for SPIF bit to go up (data sent) 
        ld    	Y,SPIDR          	; Second step to clear the SPIF bit       
read_again 
					; Generate 8 clock pulses 
        ld    	A,#$D0
        ld    	SPIDR,A           	; Send dummy value to generate the clock 
wait11  btjf  	SPICSR,#7,wait11   	; Wait for SPIF bit to go up (data sent) 

                                        ; Read data value 
	ld    	Y,SPIDR		        ; Get value from E2PROM, second step to 
	ld	A,Y			; clear SPIF
        ld    	(start,X),A       	; Store it into the 128 bytes table
        				; End of reading sequence?
                                            					 					       
        inc   	X                 	; Increment X
        cp	X,#$70                  ; 112 bytes read?
        jrult 	read_again        	; If not, still read the E2PROM, else end

      					; Deselect device 
        bset  	PBDR,#DEV_P       	; Low to high transition on the S pin for
        				; the latch 
        ret 
;******************************************************************************** 


;********************************************************************************
;+------------------------------------------------------------------------------+
;|										|
;|			STATUS REGISTER WRITE ROUTINE				|
;|										|
;+------------------------------------------------------------------------------+
;|ROUTINE DESCRIPTION:								|
;| This routine enables to write a new value into status register		|
;|										|
;|INPUT PARAMETERS:								|
;| Device pin (here 3 for PB3), new status register value			|
;|										|
;|INTERNAL PARAMETERS:								|
;| A (accumulator)								|
;|										|
;|OUTPUT PARAMETERS:								|
;| None										|
;+------------------------------------------------------------------------------+ 
.write_SR
	bres	PBDR,#DEV_P       	; Tie to low E2PROM S pin 

      					; Send write into SR instruction 
        ld    	Y,#1          
        ld    	SPIDR,Y           	; Value sent when put into the SPIDR 
wait1   btjf  	SPICSR,#7,wait1    	; Wait for SPIF bit to go up (data sent) 
        ld    	Y,SPIDR           	; Second step to clear the SPIF bit       

      					; Write into status register
        ld    	SPIDR,X           	; New value of status register = X    
wait2   btjf  	SPICSR,#7,wait2    	; Wait for SPIF bit to go up (data sent) 
        ld    	Y,SPIDR           	; Second step to clear the SPIF bit       

      					; Deselect device
        bset  	PBDR,#DEV_P  		; Low to high transition on the S pin for
        				; the latch 
        ret
;******************************************************************************** 
   
   
;********************************************************************************
;+------------------------------------------------------------------------------+
;|										|
;|			STATUS REGISTER READ ROUTINE				|
;|										|
;+------------------------------------------------------------------------------+
;|ROUTINE DESCRIPTION:								|
;| This routine enables to read the value of the status register and put it   	|
;| in SPIDR									|
;|										|
;|INPUT PARAMETERS:								|
;| Device pin (here 3 for PB3)							|
;|										|
;|INTERNAL PARAMETERS:								|
;| A (accumulator)								|
;|										|
;|OUTPUT PARAMETERS:								|
;| Status register's value							|
;+------------------------------------------------------------------------------+    
.read_SR
        bres	PBDR,#DEV_P       	; Tie to low E2PROM S pin 

      					; Send read status register instruction 
        ld    	Y,#$05 
        ld    	SPIDR,Y           	; Value sent when put into the SPIDR 
wait7   btjf  	SPICSR,#7,wait7    	; Wait for SPIF bit to go up (data sent) 
        ld    	Y,SPIDR           	; Second step to clear the SPIF bit       

      					; Generate 8 clock pulses 
        ld    	Y,#$0F
        ld    	SPIDR,Y           	; Send dummy value to generate the clock 
wait8   btjf  	SPICSR,#7,wait8    	; Wait for SPIF bit to go up (data sent) 

      					; Deselect device
	bset	PBDR,#DEV_P       	; Low to high transition on the S pin for
					; the latch 
        ret
;******************************************************************************** 


;+------------------------------------------------------------------------------+
;|	INTERRUPT SUB-ROUTINES SECTION						|
;+------------------------------------------------------------------------------+   
.dummy          iret    		; Empty subroutine 
.spi_rt         iret    		; SPI Interrupt        


;+------------------------------------------------------------------------------+
;|	INTERRUPT VECTORS MAPPING						|
;+------------------------------------------------------------------------------+   
	segment 'vectit'

                DC.W    dummy           ;FFE0-FFE1h location 
                DC.W    dummy           ;FFE2-FFE3h location
.i2c_it         DC.W    dummy           ;FFE4-FFE5h location  
                DC.W    dummy           ;FFE6-FFE7h location  
                DC.W    dummy           ;FFE8-FFE9h location  
                DC.W    dummy           ;FFEA-FFEBh location  
                DC.W    dummy           ;FFEC-FFEDh location               
.timb_it        DC.W    dummy           ;FFEE-FFEFh location
                DC.W    dummy           ;FFF0-FFF1h location                 
.tima_it        DC.W    dummy           ;FFF2-FFF3h location                       
.spi_it         DC.W    spi_rt          ;FFF4-FFF5h location  
                DC.W    dummy           ;FFF6-FFF7h location             
.ext1_it        DC.W    dummy           ;FFF8-FFF9h location 
.ext0_it        DC.W    dummy           ;FFFA-FFFBh location                      
.softit         DC.W    dummy           ;FFFC-FFFDh location                       
.reset          DC.W    main            ;FFFE-FFFFh location

	END