mouse_demo2.tan.rpt

来自「EP1C6Q240C8的examples 鼠标口测试程序」· RPT 代码 · 共 236 行 · 第 1/5 页

; Type                         ; Slack ; Required Time ; Actual Time                      ; From                             ; To                                   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------+--------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 1.984 ns                         ; ps2data                          ; mouse:mousedata|visual_0_m2_state[0] ;            ; sysclk   ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 13.022 ns                        ; segshow:showdata|visual_0_sel[0] ; seg[6]                               ; sysclk     ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.073 ns                        ; ps2data                          ; mouse:mousedata|visual_0_q[32]       ;            ; sysclk   ; 0            ;
; Clock Setup: 'sysclk'        ; N/A   ; None          ; 157.68 MHz ( period = 6.342 ns ) ; mouse:mousedata|visual_0_fall    ; mouse:mousedata|visual_0_m2_state[0] ; sysclk     ; sysclk   ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                  ;                                      ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------+--------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C6        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; sysclk          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'sysclk'                                                                                                                                                                                                                                                                                                                                                                                             ;