mouse_demo2.v

EP1C6Q240C8的examples 鼠标口测试程序

//  Library Name :  altera_demo
//  Unit    Name :  segdecode
//  Unit    Type :  Text Unit
//  
//----------------------------------------------------
 
module segdecode (datain, dataout
                  );
 
  input [3:0] datain;
  output [6:0] dataout;
 
  wire [6:0] hex;
 
  reg [6:0] visual_0_hex;
  assign hex = visual_0_hex;
 
  always @(datain)
  begin
    case (datain)          // 	 0123456
      4'b0000 :
        visual_0_hex <= 7'b0000001;
      4'b0001 :
        visual_0_hex <= 7'b1001111;
      4'b0010 :
        visual_0_hex <= 7'b0010010;
      4'b0011 :
        visual_0_hex <= 7'b0000110;
      4'b0100 :
        visual_0_hex <= 7'b1001100;
      4'b0101 :
        visual_0_hex <= 7'b0100100;
      4'b0110 :
        visual_0_hex <= 7'b0100000;
      4'b0111 :
        visual_0_hex <= 7'b0001111;
      4'b1000 :
        visual_0_hex <= 7'b0000000;
      4'b1001 :
        visual_0_hex <= 7'b0000100;
      4'b1010 :
        visual_0_hex <= 7'b0001000;
      4'b1011 :
        visual_0_hex <= 7'b1100000;
      4'b1100 :
        visual_0_hex <= 7'b0110001;
      4'b1101 :
        visual_0_hex <= 7'b1000010;
      4'b1110 :
        visual_0_hex <= 7'b0110000;
      4'b1111 :
        visual_0_hex <= 7'b0111000;
      default  :
        visual_0_hex <= 7'b1111111;
    endcase
 
  end
 
  assign dataout = hex;
 
endmodule
//--------------------------------------------------
//  
//  Library Name :  altera_demo
//  Unit    Name :  ledshow
//  Unit    Type :  Text Unit
//  
//----------------------------------------------------
 
module segshow (clk, reset, xdot, ydot, ledA1, ledA2, ledA3, ledA4, leddata
                );
 
  input clk;
  input reset;
  input [8:0] xdot;
  input [8:0] ydot;
  output ledA1;
  output ledA2;
  output ledA3;
  output ledA4;
  output [6:0] leddata;
 
  wire [1:0] sel;
  wire [3:0] data;
  wire [6:0] dataout;
 
  reg [1:0] visual_0_sel;
  assign sel = visual_0_sel;
 
  reg [3:0] visual_0_data;
  assign data = visual_0_data;
 
  reg visual_0_ledA4;
  assign ledA4 = visual_0_ledA4;
 
  reg visual_0_ledA3;
  assign ledA3 = visual_0_ledA3;
 
  reg visual_0_ledA2;
  assign ledA2 = visual_0_ledA2;
 
  reg visual_0_ledA1;
  assign ledA1 = visual_0_ledA1;
 
  always @( negedge (reset) or posedge clk )
  begin : selcount
    if ((!reset))
      visual_0_sel <= 2'b00;
    else
      visual_0_sel <= sel + 1'b1;
 
  end
 
  always @(sel or xdot or ydot)
  begin : selchoice
    visual_0_ledA1 <= 1'b0;
    visual_0_ledA2 <= 1'b0;
    visual_0_ledA3 <= 1'b0;
    visual_0_ledA4 <= 1'b0;
    case (sel)
      2'b00 :
      begin
        visual_0_ledA1 <= 1'b1;
        visual_0_data <= xdot[3:0];
      end
      2'b01 :
      begin
        visual_0_ledA2 <= 1'b1;
        visual_0_data <= xdot[7:4];
      end
      2'b10 :
      begin
        visual_0_ledA3 <= 1'b1;
        visual_0_data <= ydot[3:0];
      end
      2'b11 :
      begin
        visual_0_ledA4 <= 1'b1;
        visual_0_data <= ydot[7:4];
      end
      default  :
        visual_0_data <= 4'b0000;
    endcase
 
  end
 
 
  segdecode  decode
    (
     .datain(data),
     .dataout(dataout)
     );
  assign leddata = dataout;
 
endmodule
//--------------------------------------------------
//  
//  Library Name :  altera_demo
//  Unit    Name :  mouse
//  Unit    Type :  Text Unit
//  
//----------------------------------------------------
 
module mouse (clk, reset, ps2_clk, ps2_data, left_button, right_button, xsign,
              ysign, x_increment, y_increment, error_no_ack
              );
 
  input clk;
  input reset;
  inout ps2_clk;
  inout ps2_data;
  output left_button;
  output right_button;
  output xsign;
  output ysign;
  output [8:0] x_increment;
  output [8:0] y_increment;
  output error_no_ack;     //  Number of bits in one full packet
 
  wire reset2;
  parameter TOTAL_BITS = 	 32'd33;  //  Number of bits in one full packet
  parameter WATCHDOG = 	 32'd320;  //  Number of sys_clks for 400usec.160
  parameter DEBOUNCE_TIMER = 	 32'd4;  //  Number of sys_clks for debounce:2
  `define m1statetype_m1_clk_h	 3'd0
  `define m1statetype_m1_falling_edge	 3'd1
  `define m1statetype_m1_falling_wait	 3'd2
  `define m1statetype_m1_clk_l	 3'd3
  `define m1statetype_m1_rising_edge	 3'd4
  `define m1statetype_m1_rising_wait	 3'd5
  `define m2statetype_m2_reset	 4'd0
  `define m2statetype_m2_wait	 4'd1
  `define m2statetype_m2_gather	 4'd2
  `define m2statetype_m2_verify	 4'd3
  `define m2statetype_m2_use	 4'd4
  `define m2statetype_m2_hold_clk_l	 4'd5
  `define m2statetype_m2_data_low_1	 4'd6
  `define m2statetype_m2_data_high_1	 4'd7
  `define m2statetype_m2_data_low_2	 4'd8
  `define m2statetype_m2_data_high_2	 4'd9
  `define m2statetype_m2_data_low_3	 4'd10
  `define m2statetype_m2_data_high_3	 4'd11
  `define m2statetype_m2_error_no_ack	 4'd12
  `define m2statetype_m2_await_response	 4'd13
  wire [2:0] m1_state;
  wire [2:0] m1_next_state;
  wire [3:0] m2_state;
  wire [3:0] m2_next_state;
  wire watchdog_timer_done;// signals of commanding out to mouse
  wire debounce_timer_done;

  wire [TOTAL_BITS - 1:0] q;  // bit sequence
  wire [5:0] bitcount;     // bit count
  wire [8:0] watchdog_timer_count;  // wait time
  wire [1:0] debounce_timer_count;  // debounce time
  wire ps2_clk_hi_z;       //  Without keyboard, high Z equals 1 due to pullups.
  wire ps2_data_hi_z;      //  Without keyboard, high Z equals 1 due to pullups.
  wire clean_clk;          //  Debounced output from m1, follows ps2_clk.
  wire rise;               //  Output from m1 state machine.
  wire n_rise;
  wire fall;               //  Output from m1 state machine.
  wire n_fall;
  wire output_strobe;      //  Latches data data into the output registers
  wire packet_good;        // check the whether the data is valid
 
  reg [2:0] visual_0_m1_state;
  assign m1_state = visual_0_m1_state;
 
  reg visual_0_fall;
  assign fall = visual_0_fall;
 
  reg visual_0_rise;
  assign rise = visual_0_rise;
 
  reg [2:0] visual_0_m1_next_state;
  assign m1_next_state = visual_0_m1_next_state;
 
  reg visual_0_n_fall;
  assign n_fall = visual_0_n_fall;
 
  reg visual_0_n_rise;
  assign n_rise = visual_0_n_rise;
 
  reg visual_0_clean_clk;
  assign clean_clk = visual_0_clean_clk;
 
  reg [3:0] visual_0_m2_state;
  assign m2_state = visual_0_m2_state;
 
  reg [3:0] visual_0_m2_next_state;
  assign m2_next_state = visual_0_m2_next_state;
 
  reg visual_0_output_strobe;
  assign output_strobe = visual_0_output_strobe;
 
  reg visual_0_error_no_ack;
  assign error_no_ack = visual_0_error_no_ack;
 
  reg visual_0_ps2_data_hi_z;
  assign ps2_data_hi_z = visual_0_ps2_data_hi_z;
 
  reg visual_0_ps2_clk_hi_z;
  assign ps2_clk_hi_z = visual_0_ps2_clk_hi_z;
 
  reg [5:0] visual_0_bitcount;
  assign bitcount = visual_0_bitcount;
 
  reg [TOTAL_BITS - 1:0] visual_0_q;
  assign q = visual_0_q;
 
  reg [8:0] visual_0_watchdog_timer_count;
  assign watchdog_timer_count = visual_0_watchdog_timer_count;
 
  reg [1:0] visual_0_debounce_timer_count;
  assign debounce_timer_count = visual_0_debounce_timer_count;
 
  reg [8:0] visual_0_y_increment;
  assign y_increment = visual_0_y_increment;
 
  reg [8:0] visual_0_x_increment;
  assign x_increment = visual_0_x_increment;
 
  reg visual_0_ysign;
  assign ysign = visual_0_ysign;
 
  reg visual_0_xsign;
  assign xsign = visual_0_xsign;
 
  reg visual_0_right_button;
  assign right_button = visual_0_right_button;
 
  reg visual_0_left_button;
  assign left_button = visual_0_left_button;
 
  assign ps2_clk = (ps2_clk_hi_z == 1'b0 ? 1'b0 : 1'bz);
  assign ps2_data = (ps2_data_hi_z == 1'b0 ? 1'b0 : 1'bz);
  // -------------m1 state State register
  always @( negedge (reset) or posedge clk )
  begin : m1statechg
    if ((!reset))
    begin
      visual_0_rise <= 1'b0;
      visual_0_fall <= 1'b0;
      visual_0_m1_state <= `m1statetype_m1_clk_h;
                           // clean_clk <= '0';
    end
    else
    begin
      visual_0_m1_state <= m1_next_state;
      visual_0_rise <= n_rise;
      visual_0_fall <= n_fall;
    end
 
  end
 
  always @(m1_state or ps2_clk or debounce_timer_done)
  begin : m1statetr
    visual_0_clean_clk <= 1'b0;
    visual_0_n_rise <= 1'b0;
    visual_0_n_fall <= 1'b0;
    case (m1_state)
      `m1statetype_m1_clk_h :
      begin
        visual_0_clean_clk <= 1'b1;
        if ((!ps2_clk))
          visual_0_m1_next_state <= `m1statetype_m1_falling_edge;
        else
          visual_0_m1_next_state <= `m1statetype_m1_clk_h;
 
      end
      `m1statetype_m1_falling_edge :
      begin
        visual_0_n_fall <= 1'b1;
        visual_0_m1_next_state <= `m1statetype_m1_falling_wait;  // m1_next_state <= m1_falling_wait;
      end
      `m1statetype_m1_falling_wait :
        if ((debounce_timer_done))
          visual_0_m1_next_state <= `m1statetype_m1_clk_l;
        else
          visual_0_m1_next_state <= `m1statetype_m1_falling_wait;
 
      `m1statetype_m1_clk_l :
        if ((ps2_clk))
          visual_0_m1_next_state <= `m1statetype_m1_rising_edge;
        else
          visual_0_m1_next_state <= `m1statetype_m1_clk_l;