flash3.tan.rpt

EP1C6Q240C8的examples flash测试程序

; Worst-case tsu                              ; N/A   ; None          ; 4.575 ns                         ; altera_internal_jtag~SHIFTUSER                ; FOR_HT3:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 7.784 ns                         ; FOR_HT3:inst|led_pio:the_led_pio|data_out[0]  ; LED[0]                                                                                                                                                                                           ; CLK                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                      ; altera_reserved_tdo                                                                                                                                                                              ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.667 ns                         ; altera_internal_jtag                          ; sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]                                                                                                                                          ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLK'                          ; N/A   ; None          ; 36.73 MHz ( period = 27.224 ns ) ; FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[16]         ; FOR_HT3:inst|cpu_0:the_cpu_0|av_ld_byte1_data[4]                                                                                                                                                 ; CLK                          ; CLK                          ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 89.81 MHz ( period = 11.134 ns ) ; sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] ; FOR_HT3:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[13] ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                               ;                                                                                                                                                                                                  ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                               ;
+---------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name                 ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+---------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK                             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; altera_internal_jtag~UPDATEUSER ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; altera_internal_jtag~TCKUTAP    ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+---------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------+--------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                       ; To                                               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------+--------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+