flash3.map.eqn

EP1C6Q240C8的examples flash测试程序

--E1_R_ctrl_br is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_br
--operation mode is normal

E1_R_ctrl_br = AMPP_FUNCTION(CLK, E1_D_iw[1], E1_D_iw[2], E1_D_iw[0], D1_data_out);


--E1L063 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc_sel_nxt[0]~53
--operation mode is normal

E1L063 = AMPP_FUNCTION(E1_W_cmp_result, E1_R_ctrl_br);


--E1_R_ctrl_uncond_cti is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_uncond_cti
--operation mode is normal

E1_R_ctrl_uncond_cti = AMPP_FUNCTION(CLK, E1L73, E1L52, E1_D_op_eret, E1_D_op_bret, D1_data_out);


--E1L163 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc_sel_nxt[0]~54
--operation mode is normal

E1L163 = AMPP_FUNCTION(E1_R_ctrl_break, E1L063, E1_R_ctrl_uncond_cti, E1_R_ctrl_exception);


--E1_W_valid is FOR_HT3:inst|cpu_0:the_cpu_0|W_valid
--operation mode is normal

E1_W_valid = AMPP_FUNCTION(CLK, E1_E_valid, E1L762, D1_data_out);


--H1_d1_reasons_to_wait is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_reasons_to_wait
--operation mode is normal

H1_d1_reasons_to_wait_lut_out = H1L12;
H1_d1_reasons_to_wait = DFFEAS(H1_d1_reasons_to_wait_lut_out, CLK, D1_data_out, , , , , , );


--H1_cpu_0_jtag_debug_module_arb_addend[1] is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[1]
--operation mode is normal

H1_cpu_0_jtag_debug_module_arb_addend[1]_lut_out = H1L12 & H1L32 # !H1L12 & H1L22 # !H1L32 & H1_cpu_0_jtag_debug_module_saved_chosen_master_vector[0];
H1_cpu_0_jtag_debug_module_arb_addend[1] = DFFEAS(H1_cpu_0_jtag_debug_module_arb_addend[1]_lut_out, CLK, D1_data_out, , H1L72, , , , );


--P1L7 is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_requests_onchip_memory_0_s1~295
--operation mode is normal

P1L7 = !E1_F_pc[18] & !E1_F_pc[17] & !E1_i_read & !E1_F_pc[19];


--P1L8 is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_requests_onchip_memory_0_s1~296
--operation mode is normal

P1L8 = !E1_F_pc[16] & !E1_F_pc[15] & !E1_F_pc[14] & !E1_F_pc[13];


--P1L9 is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_requests_onchip_memory_0_s1~297
--operation mode is normal

P1L9 = P1L7 & P1L8 & !E1_F_pc[12] & !E1_F_pc[11];


--H1L3 is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~237
--operation mode is normal

H1L3 = E1_F_pc[10] & P1L9 & !E1_F_pc[9];


--H1_cpu_0_jtag_debug_module_arb_addend[0] is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0]
--operation mode is normal

H1_cpu_0_jtag_debug_module_arb_addend[0]_lut_out = H1L22 & !H1L12 # !H1L22 & H1L12 # !H1L32 & H1_cpu_0_jtag_debug_module_saved_chosen_master_vector[0];
H1_cpu_0_jtag_debug_module_arb_addend[0] = DFFEAS(H1_cpu_0_jtag_debug_module_arb_addend[0]_lut_out, CLK, D1_data_out, , H1L72, , , , );


--J1L53 is FOR_HT3:inst|jtag_uart:the_jtag_uart|av_waitrequest~0
--operation mode is normal

J1L53 = E1_d_read # W1_d_write;


--H1_cpu_0_data_master_requests_cpu_0_jtag_debug_module is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_data_master_requests_cpu_0_jtag_debug_module
--operation mode is normal

H1_cpu_0_data_master_requests_cpu_0_jtag_debug_module = E1_W_alu_result[12] & J1L53 & R1L3 & !E1_W_alu_result[11];


--H1L1 is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|add~349
--operation mode is normal

H1L1 = H1_cpu_0_jtag_debug_module_arb_addend[1] & !H1L3 & !H1_cpu_0_jtag_debug_module_arb_addend[0] # !H1_cpu_0_data_master_requests_cpu_0_jtag_debug_module # !H1_cpu_0_jtag_debug_module_arb_addend[1] & !H1L3 & !H1_cpu_0_jtag_debug_module_arb_addend[0] & !H1_cpu_0_data_master_requests_cpu_0_jtag_debug_module;


--G1L11 is FOR_HT3:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~44
--operation mode is normal

G1L11 = H1_d1_reasons_to_wait & H1L1 # !H1_cpu_0_jtag_debug_module_arb_addend[0] # !H1L3;


--G1L21 is FOR_HT3:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~45
--operation mode is normal

G1L21 = E1_i_read # S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1] & G1_cpu_0_instruction_master_dbs_address[1] # !E1_F_pc[19];


--P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register
--operation mode is normal

P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register_lut_out = P1L32;
P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register = DFFEAS(P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register_lut_out, CLK, D1_data_out, , , , , , );


--P1L5 is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_qualified_request_onchip_memory_0_s1~22
--operation mode is normal

P1L5 = P1L9 & !E1_F_pc[10] & E1_i_read # !P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register;


--G1L31 is FOR_HT3:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~46
--operation mode is normal

G1L31 = G1L11 & G1L21 & !S1L12 & !P1L5;


--S1_cfi_flash_s1_wait_counter[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_wait_counter[0]
--operation mode is normal

S1_cfi_flash_s1_wait_counter[0]_lut_out = !S1_cfi_flash_s1_wait_counter[0] & S1L3;
S1_cfi_flash_s1_wait_counter[0] = DFFEAS(S1_cfi_flash_s1_wait_counter[0]_lut_out, CLK, D1_data_out, , , , , , );


--S1L86 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|reduce_nor~2
--operation mode is normal

S1L86 = S1_cfi_flash_s1_wait_counter[3] # S1_cfi_flash_s1_wait_counter[2] # S1_cfi_flash_s1_wait_counter[1] # S1_cfi_flash_s1_wait_counter[0];


--S1L99 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~21
--operation mode is normal

S1L99 = S1L86 # !S1_d1_reasons_to_wait & S1L12 # S1L51;


--S1L101 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_firsttransfer~84
--operation mode is normal

S1L101 = S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 & S1_cpu_0_data_master_requests_cfi_flash_s1 # S1L52 & S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 # !S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 & S1L52 & S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1;


--S1L69 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[0]~31
--operation mode is normal

S1L69 = S1L6 & !S1L101 # !S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable # !S1L6 & S1L201 & !S1L101 # !S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable;


--S1L001 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~22
--operation mode is normal

S1L001 = S1_cfi_flash_s1_in_a_read_cycle & S1L89 # S1L86 # !S1_cfi_flash_s1_in_a_read_cycle & S1_cfi_flash_s1_in_a_write_cycle & S1L89 # S1L86;


--S1L1 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|always3~15
--operation mode is normal

S1L1 = !S1L001 & S1L12 # S1L51;


--S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1]
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1]_lut_out = S1L201;
S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] = DFFEAS(S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1]_lut_out, CLK, D1_data_out, , S1L69, , , , );


--S1L36 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1~130
--operation mode is normal

S1L36 = S1L69 & S1L201 # !S1L69 & S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1];


--S1L46 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1~131
--operation mode is normal

S1L46 = S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable & S1L101 # !S1L89;


--E1_E_new_inst is FOR_HT3:inst|cpu_0:the_cpu_0|E_new_inst
--operation mode is normal

E1_E_new_inst = AMPP_FUNCTION(CLK, E1_R_valid, D1_data_out);


--E1_R_ctrl_ld is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_ld
--operation mode is normal

E1_R_ctrl_ld = AMPP_FUNCTION(CLK, E1_D_iw[0], E1_D_iw[1], E1_D_iw[2], E1_D_iw[4], D1_data_out);


--E1_R_ctrl_st is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_st
--operation mode is normal

E1_R_ctrl_st = AMPP_FUNCTION(CLK, E1_D_iw[0], E1_D_iw[1], D1_data_out);


--E1_d_write_nxt is FOR_HT3:inst|cpu_0:the_cpu_0|d_write_nxt
--operation mode is normal

E1_d_write_nxt = AMPP_FUNCTION(E1_E_new_inst, E1_R_ctrl_st, W1_d_write, F1_cpu_0_data_master_waitrequest);


--E1_R_logic_op[1] is FOR_HT3:inst|cpu_0:the_cpu_0|R_logic_op[1]
--operation mode is normal

E1_R_logic_op[1] = AMPP_FUNCTION(CLK, E1L3, E1L28, E1L7, E1L4, D1_data_out);


--E1_E_src2[21] is FOR_HT3:inst|cpu_0:the_cpu_0|E_src2[21]
--operation mode is normal

E1_E_src2[21] = AMPP_FUNCTION(CLK, Z1_q_b[21], E1_D_iw[21], E1_D_iw[11], E1_R_src2_use_imm, D1_data_out, E1L993, E1_R_ctrl_hi_imm);


--E1_E_src1[21] is FOR_HT3:inst|cpu_0:the_cpu_0|E_src1[21]
--operation mode is normal

E1_E_src1[21] = AMPP_FUNCTION(CLK, E1_D_iw[25], Z1_q_a[21], E1L815, E1L793, D1_data_out, E1L693);


--E1_R_logic_op[0] is FOR_HT3:inst|cpu_0:the_cpu_0|R_logic_op[0]
--operation mode is normal

E1_R_logic_op[0] = AMPP_FUNCTION(CLK, E1L3, E1L18, E1L7, E1L4, D1_data_out);


--E1L041 is FOR_HT3:inst|cpu_0:the_cpu_0|E_logic_result[21]~8237
--operation mode is normal

E1L041 = AMPP_FUNCTION(E1_R_logic_op[1], E1_E_src2[21], E1_E_src1[21], E1_R_logic_op[0]);


--E1_E_shift_rot_result[21] is FOR_HT3:inst|cpu_0:the_cpu_0|E_shift_rot_result[21]
--operation mode is normal

E1_E_shift_rot_result[21] = AMPP_FUNCTION(CLK, E1_E_shift_rot_result[20], E1_E_shift_rot_result[22], E1_E_src1[21], E1_R_ctrl_shift_rot_right, D1_data_out, E1_E_new_inst);


--E1_R_ctrl_dst_data_sel_logic_result is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_dst_data_sel_logic_result
--operation mode is normal

E1_R_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(CLK, E1L53, E1L39, E1_D_iw[11], E1L51, D1_data_out);


--E1_R_ctrl_dst_data_sel_cmp is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_dst_data_sel_cmp
--operation mode is normal

E1_R_ctrl_dst_data_sel_cmp = AMPP_FUNCTION(CLK, E1L88, E1L19, E1L31, E1L41, D1_data_out);


--E1_R_ctrl_rdctl_inst is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_rdctl_inst
--operation mode is normal

E1_R_ctrl_rdctl_inst = AMPP_FUNCTION(CLK, E1_D_iw[15], E1_D_iw[16], E1L29, E1L297, D1_data_out);


--E1L001 is FOR_HT3:inst|cpu_0:the_cpu_0|E_alu_result~0
--operation mode is normal

E1L001 = AMPP_FUNCTION(E1_R_ctrl_dst_data_sel_cmp, E1_R_ctrl_rdctl_inst);


--E1_R_ctrl_shift_rot is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_shift_rot
--operation mode is normal

E1_R_ctrl_shift_rot = AMPP_FUNCTION(CLK, E1_D_iw[12], E1L29, E1_D_iw[13], D1_data_out);


--S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0]
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0]_lut_out = S1L6;
S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] = DFFEAS(S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0]_lut_out, CLK, D1_data_out, , S1L69, , , , );


--S1L79 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_winner[0]~20
--operation mode is normal

S1L79 = S1L69 & S1L6 # !S1L69 & S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0];


--E1_D_iw[4] is FOR_HT3:inst|cpu_0:the_cpu_0|D_iw[4]
--operation mode is normal

E1_D_iw[4] = AMPP_FUNCTION(CLK, E1L772, V1L8, H1L3, E1L45, D1_data_out, E1_F_valid);


--E1L915 is FOR_HT3:inst|cpu_0:the_cpu_0|add~947
--operation mode is arithmetic

E1L915 = AMPP_FUNCTION(E1_E_src2[0], E1_E_src1[0]);

--E1L025 is FOR_HT3:inst|cpu_0:the_cpu_0|add~947COUT
--operation mode is arithmetic

E1L025 = AMPP_FUNCTION(E1_E_src2[0], E1_E_src1[0]);


--E1L485 is FOR_HT3:inst|cpu_0:the_cpu_0|add~980