flash3.map.eqn

EP1C6Q240C8的examples flash测试程序

S1L52 = E1_F_pc[19] & !E1_i_read;


--S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1
--operation mode is normal

S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1_lut_out = S1L52 & S1L79 # S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 & S1L46;
S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 = DFFEAS(S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1_lut_out, CLK, D1_data_out, , , , , , );


--S1L41 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_s1~135
--operation mode is normal

S1L41 = S1L31 & !S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 # !S1L52 # !S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable;


--E1_d_byteenable[1] is FOR_HT3:inst|cpu_0:the_cpu_0|d_byteenable[1]
--operation mode is normal

E1_d_byteenable[1] = AMPP_FUNCTION(CLK, E1_D_iw[4], E1L201, E1_D_iw[3], E1L301, D1_data_out);


--E1_d_byteenable[0] is FOR_HT3:inst|cpu_0:the_cpu_0|d_byteenable[0]
--operation mode is normal

E1_d_byteenable[0] = AMPP_FUNCTION(CLK, E1_D_iw[4], E1_D_iw[3], E1L201, E1L301, D1_data_out);


--S1L96 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|reduce_nor~124
--operation mode is normal

S1L96 = E1_d_byteenable[1] # E1_d_byteenable[0];


--F1_cpu_0_data_master_dbs_address[1] is FOR_HT3:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1]
--operation mode is normal

F1_cpu_0_data_master_dbs_address[1]_lut_out = !F1_cpu_0_data_master_dbs_address[1];
F1_cpu_0_data_master_dbs_address[1] = DFFEAS(F1_cpu_0_data_master_dbs_address[1]_lut_out, CLK, D1_data_out, , F1L4, , , , );


--E1_d_byteenable[3] is FOR_HT3:inst|cpu_0:the_cpu_0|d_byteenable[3]
--operation mode is normal

E1_d_byteenable[3] = AMPP_FUNCTION(CLK, E1_D_iw[4], E1L201, E1L301, E1_D_iw[3], D1_data_out);


--E1_d_byteenable[2] is FOR_HT3:inst|cpu_0:the_cpu_0|d_byteenable[2]
--operation mode is normal

E1_d_byteenable[2] = AMPP_FUNCTION(CLK, E1_D_iw[4], E1_D_iw[3], E1L301, E1L201, D1_data_out);


--S1L07 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|reduce_nor~125
--operation mode is normal

S1L07 = F1_cpu_0_data_master_dbs_address[1] & E1_d_byteenable[3] # E1_d_byteenable[2] # !F1_cpu_0_data_master_dbs_address[1] & S1L96;


--F1_cpu_0_data_master_no_byte_enables_and_last_term is FOR_HT3:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_no_byte_enables_and_last_term
--operation mode is normal

F1_cpu_0_data_master_no_byte_enables_and_last_term_lut_out = F1_last_dbs_term_and_run;
F1_cpu_0_data_master_no_byte_enables_and_last_term = DFFEAS(F1_cpu_0_data_master_no_byte_enables_and_last_term_lut_out, CLK, D1_data_out, , , , , , );


--S1L51 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_s1~136
--operation mode is normal

S1L51 = S1L41 & S1L07 & !F1_cpu_0_data_master_no_byte_enables_and_last_term # !W1_d_write;


--S1_tri_state_bridge_0_avalon_slave_arb_addend[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_arb_addend[0]_lut_out = S1L001 & !S1L6 # !S1L001 & S1L69 & S1L6 # !S1L69 & S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0];
S1_tri_state_bridge_0_avalon_slave_arb_addend[0] = DFFEAS(S1_tri_state_bridge_0_avalon_slave_arb_addend[0]_lut_out, CLK, D1_data_out, , S1L66, , , , );


--S1L6 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_in_a_read_cycle~49
--operation mode is normal

S1L6 = S1L12 & S1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !S1L51 # !S1_tri_state_bridge_0_avalon_slave_arb_addend[0];


--S1L201 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~56
--operation mode is normal

S1L201 = S1L51 & S1_tri_state_bridge_0_avalon_slave_arb_addend[1] # !S1L12 & !S1_tri_state_bridge_0_avalon_slave_arb_addend[0];


--S1_cfi_flash_s1_in_a_read_cycle is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_in_a_read_cycle
--operation mode is normal

S1_cfi_flash_s1_in_a_read_cycle = S1L6 # E1_d_read & S1L201;


--S1_cfi_flash_s1_wait_counter[3] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_wait_counter[3]
--operation mode is normal

S1_cfi_flash_s1_wait_counter[3]_lut_out = S1L4 # S1L89 & S1_cfi_flash_s1_in_a_read_cycle # S1_cfi_flash_s1_in_a_write_cycle;
S1_cfi_flash_s1_wait_counter[3] = DFFEAS(S1_cfi_flash_s1_wait_counter[3]_lut_out, CLK, D1_data_out, , , , , , );


--S1_d1_reasons_to_wait is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait
--operation mode is normal

S1_d1_reasons_to_wait_lut_out = S1L001;
S1_d1_reasons_to_wait = DFFEAS(S1_d1_reasons_to_wait_lut_out, CLK, D1_data_out, , , , , , );


--S1L89 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_begins_xfer~40
--operation mode is normal

S1L89 = !S1_d1_reasons_to_wait & S1L12 # S1L51;


--D1_data_out is FOR_HT3:inst|reset_clk_domain_synch_module:reset_clk_domain_synch|data_out
--operation mode is normal

D1_data_out_lut_out = D1_p1_data_out;
D1_data_out = DFFEAS(D1_data_out_lut_out, CLK, !B1L1, , , , , , );


--S1_cfi_flash_s1_in_a_write_cycle is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_in_a_write_cycle
--operation mode is normal

S1_cfi_flash_s1_in_a_write_cycle = W1_d_write & S1L201;


--S1_cfi_flash_s1_wait_counter[2] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_wait_counter[2]
--operation mode is normal

S1_cfi_flash_s1_wait_counter[2]_lut_out = S1L3 & S1_cfi_flash_s1_wait_counter[2] $ (!S1_cfi_flash_s1_wait_counter[1] & !S1_cfi_flash_s1_wait_counter[0]);
S1_cfi_flash_s1_wait_counter[2] = DFFEAS(S1_cfi_flash_s1_wait_counter[2]_lut_out, CLK, D1_data_out, , , , , , );


--S1_cfi_flash_s1_wait_counter[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_wait_counter[1]
--operation mode is normal

S1_cfi_flash_s1_wait_counter[1]_lut_out = S1L89 & !S1_cfi_flash_s1_in_a_read_cycle & S1L2 # S1_cfi_flash_s1_in_a_write_cycle # !S1L89 & S1L2;
S1_cfi_flash_s1_wait_counter[1] = DFFEAS(S1_cfi_flash_s1_wait_counter[1]_lut_out, CLK, D1_data_out, , , , , , );


--S1L76 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash~106
--operation mode is normal

S1L76 = !S1_cfi_flash_s1_wait_counter[2] & !S1_cfi_flash_s1_wait_counter[1];


--S1L66 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_select_n_to_the_cfi_flash~0
--operation mode is normal

S1L66 = S1_tri_state_bridge_0_avalon_slave_arb_addend[1] & S1L12 # S1L51 # !S1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !S1_tri_state_bridge_0_avalon_slave_arb_addend[0] & S1L12 # S1L51;


--E1_W_alu_result[20] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[20]
--operation mode is normal

E1_W_alu_result[20] = AMPP_FUNCTION(CLK, E1L931, E1L753, E1_E_shift_rot_result[20], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L753 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[18]~COMBOUT
--operation mode is normal

E1L753 = AMPP_FUNCTION(E1L426, E1L955, E1_E_alu_sub);

--E1_F_pc[18] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[18]
--operation mode is normal

E1_F_pc[18] = AMPP_FUNCTION(CLK, E1L426, E1L955, E1L615, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[19] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[19]
--operation mode is normal

E1_W_alu_result[19] = AMPP_FUNCTION(CLK, E1L831, E1L553, E1_E_shift_rot_result[19], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L553 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[17]~COMBOUT
--operation mode is normal

E1L553 = AMPP_FUNCTION(E1L226, E1L755, E1_E_alu_sub);

--E1_F_pc[17] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[17]
--operation mode is normal

E1_F_pc[17] = AMPP_FUNCTION(CLK, E1L226, E1L755, E1L415, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[18] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[18]
--operation mode is normal

E1_W_alu_result[18] = AMPP_FUNCTION(CLK, E1L731, E1L353, E1_E_shift_rot_result[18], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L353 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[16]~COMBOUT
--operation mode is normal

E1L353 = AMPP_FUNCTION(E1L026, E1L555, E1_E_alu_sub);

--E1_F_pc[16] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[16]
--operation mode is normal

E1_F_pc[16] = AMPP_FUNCTION(CLK, E1L026, E1L555, E1L215, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[17] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[17]
--operation mode is normal

E1_W_alu_result[17] = AMPP_FUNCTION(CLK, E1L631, E1L153, E1_E_shift_rot_result[17], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L153 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[15]~COMBOUT
--operation mode is normal

E1L153 = AMPP_FUNCTION(E1L816, E1L355, E1_E_alu_sub);

--E1_F_pc[15] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[15]
--operation mode is normal

E1_F_pc[15] = AMPP_FUNCTION(CLK, E1L816, E1L355, E1L015, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[16] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[16]
--operation mode is normal

E1_W_alu_result[16] = AMPP_FUNCTION(CLK, E1L531, E1L943, E1_E_shift_rot_result[16], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L943 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[14]~COMBOUT
--operation mode is normal

E1L943 = AMPP_FUNCTION(E1L616, E1L155, E1_E_alu_sub);

--E1_F_pc[14] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[14]
--operation mode is normal

E1_F_pc[14] = AMPP_FUNCTION(CLK, E1L616, E1L155, E1L805, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[15] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[15]
--operation mode is normal

E1_W_alu_result[15] = AMPP_FUNCTION(CLK, E1L431, E1L743, E1_E_shift_rot_result[15], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L743 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[13]~COMBOUT
--operation mode is normal

E1L743 = AMPP_FUNCTION(E1L416, E1L945, E1_E_alu_sub);

--E1_F_pc[13] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[13]
--operation mode is normal

E1_F_pc[13] = AMPP_FUNCTION(CLK, E1L416, E1L945, E1L605, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[14] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[14]
--operation mode is normal

E1_W_alu_result[14] = AMPP_FUNCTION(CLK, E1L331, E1L543, E1_E_shift_rot_result[14], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L543 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[12]~COMBOUT
--operation mode is normal

E1L543 = AMPP_FUNCTION(E1L216, E1L745, E1_E_alu_sub);

--E1_F_pc[12] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[12]
--operation mode is normal

E1_F_pc[12] = AMPP_FUNCTION(CLK, E1L216, E1L745, E1L405, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[13] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[13]
--operation mode is normal

E1_W_alu_result[13] = AMPP_FUNCTION(CLK, E1L231, E1L343, E1_E_shift_rot_result[13], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L343 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[11]~COMBOUT
--operation mode is normal

E1L343 = AMPP_FUNCTION(E1L016, E1L545, E1_E_alu_sub);

--E1_F_pc[11] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[11]
--operation mode is normal

E1_F_pc[11] = AMPP_FUNCTION(CLK, E1L016, E1L545, E1L205, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[12] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[12]
--operation mode is normal

E1_W_alu_result[12] = AMPP_FUNCTION(CLK, E1L131, E1L501, E1_E_shift_rot_result[12], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1_F_pc[10] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[10]
--operation mode is normal

E1_F_pc[10] = AMPP_FUNCTION(CLK, E1_R_ctrl_break, E1L953, E1_R_ctrl_exception, D1_data_out, E1_W_valid);


--E1_W_alu_result[11] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[11]
--operation mode is normal

E1_W_alu_result[11] = AMPP_FUNCTION(CLK, E1L031, E1L043, E1_E_shift_rot_result[11], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);