flash3.map.eqn

EP1C6Q240C8的examples flash测试程序

--S1_tri_state_bridge_0_readn is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn
--operation mode is normal

S1_tri_state_bridge_0_readn_lut_out = S1_cfi_flash_s1_in_a_read_cycle & !S1_cfi_flash_s1_wait_counter[3] & !S1L89;
S1_tri_state_bridge_0_readn = DFFEAS(S1_tri_state_bridge_0_readn_lut_out, CLK, D1_data_out, , , , , , );


--S1_write_n_to_the_cfi_flash is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash
--operation mode is normal

S1_write_n_to_the_cfi_flash_lut_out = S1_cfi_flash_s1_in_a_write_cycle & !S1L89 & S1_cfi_flash_s1_wait_counter[3] $ !S1L76;
S1_write_n_to_the_cfi_flash = DFFEAS(S1_write_n_to_the_cfi_flash_lut_out, CLK, D1_data_out, , , , , , );


--S1_select_n_to_the_cfi_flash is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash
--operation mode is normal

S1_select_n_to_the_cfi_flash_lut_out = S1L66;
S1_select_n_to_the_cfi_flash = DFFEAS(S1_select_n_to_the_cfi_flash_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[20] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[20]
--operation mode is normal

S1_tri_state_bridge_0_address[20]_lut_out = S1L201 & E1_W_alu_result[20] # !S1L201 & E1_F_pc[18];
S1_tri_state_bridge_0_address[20] = DFFEAS(S1_tri_state_bridge_0_address[20]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[19] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[19]
--operation mode is normal

S1_tri_state_bridge_0_address[19]_lut_out = S1L201 & E1_W_alu_result[19] # !S1L201 & E1_F_pc[17];
S1_tri_state_bridge_0_address[19] = DFFEAS(S1_tri_state_bridge_0_address[19]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[18] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[18]
--operation mode is normal

S1_tri_state_bridge_0_address[18]_lut_out = S1L201 & E1_W_alu_result[18] # !S1L201 & E1_F_pc[16];
S1_tri_state_bridge_0_address[18] = DFFEAS(S1_tri_state_bridge_0_address[18]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[17] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[17]
--operation mode is normal

S1_tri_state_bridge_0_address[17]_lut_out = S1L201 & E1_W_alu_result[17] # !S1L201 & E1_F_pc[15];
S1_tri_state_bridge_0_address[17] = DFFEAS(S1_tri_state_bridge_0_address[17]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[16] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[16]
--operation mode is normal

S1_tri_state_bridge_0_address[16]_lut_out = S1L201 & E1_W_alu_result[16] # !S1L201 & E1_F_pc[14];
S1_tri_state_bridge_0_address[16] = DFFEAS(S1_tri_state_bridge_0_address[16]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[15] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[15]
--operation mode is normal

S1_tri_state_bridge_0_address[15]_lut_out = S1L201 & E1_W_alu_result[15] # !S1L201 & E1_F_pc[13];
S1_tri_state_bridge_0_address[15] = DFFEAS(S1_tri_state_bridge_0_address[15]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[14] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[14]
--operation mode is normal

S1_tri_state_bridge_0_address[14]_lut_out = S1L201 & E1_W_alu_result[14] # !S1L201 & E1_F_pc[12];
S1_tri_state_bridge_0_address[14] = DFFEAS(S1_tri_state_bridge_0_address[14]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[13] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[13]
--operation mode is normal

S1_tri_state_bridge_0_address[13]_lut_out = S1L201 & E1_W_alu_result[13] # !S1L201 & E1_F_pc[11];
S1_tri_state_bridge_0_address[13] = DFFEAS(S1_tri_state_bridge_0_address[13]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[12] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[12]
--operation mode is normal

S1_tri_state_bridge_0_address[12]_lut_out = S1L201 & E1_W_alu_result[12] # !S1L201 & E1_F_pc[10];
S1_tri_state_bridge_0_address[12] = DFFEAS(S1_tri_state_bridge_0_address[12]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[11] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[11]
--operation mode is normal

S1_tri_state_bridge_0_address[11]_lut_out = S1L201 & E1_W_alu_result[11] # !S1L201 & E1_F_pc[9];
S1_tri_state_bridge_0_address[11] = DFFEAS(S1_tri_state_bridge_0_address[11]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[10] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[10]
--operation mode is normal

S1_tri_state_bridge_0_address[10]_lut_out = S1L201 & E1_W_alu_result[10] # !S1L201 & E1_F_pc[8];
S1_tri_state_bridge_0_address[10] = DFFEAS(S1_tri_state_bridge_0_address[10]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[9] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[9]
--operation mode is normal

S1_tri_state_bridge_0_address[9]_lut_out = S1L201 & E1_W_alu_result[9] # !S1L201 & E1_F_pc[7];
S1_tri_state_bridge_0_address[9] = DFFEAS(S1_tri_state_bridge_0_address[9]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[8] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[8]
--operation mode is normal

S1_tri_state_bridge_0_address[8]_lut_out = S1L201 & E1_W_alu_result[8] # !S1L201 & E1_F_pc[6];
S1_tri_state_bridge_0_address[8] = DFFEAS(S1_tri_state_bridge_0_address[8]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[7] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7]
--operation mode is normal

S1_tri_state_bridge_0_address[7]_lut_out = S1L201 & E1_W_alu_result[7] # !S1L201 & E1_F_pc[5];
S1_tri_state_bridge_0_address[7] = DFFEAS(S1_tri_state_bridge_0_address[7]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[6] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[6]
--operation mode is normal

S1_tri_state_bridge_0_address[6]_lut_out = S1L201 & E1_W_alu_result[6] # !S1L201 & E1_F_pc[4];
S1_tri_state_bridge_0_address[6] = DFFEAS(S1_tri_state_bridge_0_address[6]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[5] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[5]
--operation mode is normal

S1_tri_state_bridge_0_address[5]_lut_out = S1L201 & E1_W_alu_result[5] # !S1L201 & E1_F_pc[3];
S1_tri_state_bridge_0_address[5] = DFFEAS(S1_tri_state_bridge_0_address[5]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[4] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[4]
--operation mode is normal

S1_tri_state_bridge_0_address[4]_lut_out = S1L201 & E1_W_alu_result[4] # !S1L201 & E1_F_pc[2];
S1_tri_state_bridge_0_address[4] = DFFEAS(S1_tri_state_bridge_0_address[4]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[3] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[3]
--operation mode is normal

S1_tri_state_bridge_0_address[3]_lut_out = S1L201 & E1_W_alu_result[3] # !S1L201 & E1_F_pc[1];
S1_tri_state_bridge_0_address[3] = DFFEAS(S1_tri_state_bridge_0_address[3]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[2] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[2]
--operation mode is normal

S1_tri_state_bridge_0_address[2]_lut_out = S1L201 & E1_W_alu_result[2] # !S1L201 & E1_F_pc[0];
S1_tri_state_bridge_0_address[2] = DFFEAS(S1_tri_state_bridge_0_address[2]_lut_out, CLK, D1_data_out, , , , , , );


--S1_tri_state_bridge_0_address[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[1]
--operation mode is normal

S1_tri_state_bridge_0_address[1]_lut_out = S1L201 & F1_cpu_0_data_master_dbs_address[1] # !S1L201 & G1_cpu_0_instruction_master_dbs_address[1];
S1_tri_state_bridge_0_address[1] = DFFEAS(S1_tri_state_bridge_0_address[1]_lut_out, CLK, D1_data_out, , , , , , );


--L1_data_out[2] is FOR_HT3:inst|led_pio:the_led_pio|data_out[2]
--operation mode is normal

L1_data_out[2]_lut_out = E1_d_writedata[2];
L1_data_out[2] = DFFEAS(L1_data_out[2]_lut_out, CLK, D1_data_out, , L1L1, , , , );


--L1_data_out[1] is FOR_HT3:inst|led_pio:the_led_pio|data_out[1]
--operation mode is normal

L1_data_out[1]_lut_out = E1_d_writedata[1];
L1_data_out[1] = DFFEAS(L1_data_out[1]_lut_out, CLK, D1_data_out, , L1L1, , , , );


--L1_data_out[0] is FOR_HT3:inst|led_pio:the_led_pio|data_out[0]
--operation mode is normal

L1_data_out[0]_lut_out = E1_d_writedata[0];
L1_data_out[0] = DFFEAS(L1_data_out[0]_lut_out, CLK, D1_data_out, , L1L1, , , , );


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L4 is altera_internal_jtag~SHIFTUSER
A1L4 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L8 is altera_internal_jtag~UPDATEUSER
A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L3 is altera_internal_jtag~RUNIDLEUSER
A1L3 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);


--E1_F_pc[19] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[19]
--operation mode is normal

E1_F_pc[19] = AMPP_FUNCTION(CLK, E1L263, E1L815, E1L601, E1L163, D1_data_out, E1_W_valid);


--E1_i_read is FOR_HT3:inst|cpu_0:the_cpu_0|i_read
--operation mode is normal

E1_i_read = AMPP_FUNCTION(CLK, E1_W_valid, E1_i_read, G1L31, D1_data_out);


--S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1]
--operation mode is normal

S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1]_lut_out = S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0];
S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1] = DFFEAS(S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1]_lut_out, CLK, D1_data_out, , , , , , );


--S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0]
--operation mode is normal

S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0]_lut_out = S1L6 & !S1L99;
S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0] = DFFEAS(S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0]_lut_out, CLK, D1_data_out, , , , , , );


--S1L02 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_s1~57
--operation mode is normal

S1L02 = E1_F_pc[19] & !E1_i_read & !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1] & !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0];


--S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable_lut_out = S1L69;
S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable = DFFEAS(S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable_lut_out, CLK, D1_data_out, , S1L1, , , , );


--S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1
--operation mode is normal

S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1_lut_out = S1_cpu_0_data_master_requests_cfi_flash_s1 & S1L36 # S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 & S1L46;
S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 = DFFEAS(S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1_lut_out, CLK, D1_data_out, , , , , , );


--E1_d_read is FOR_HT3:inst|cpu_0:the_cpu_0|d_read
--operation mode is normal

E1_d_read = AMPP_FUNCTION(CLK, E1_E_new_inst, E1_R_ctrl_ld, E1_d_read, F1_cpu_0_data_master_waitrequest, D1_data_out);


--W1_d_write is FOR_HT3:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|d_write
--operation mode is normal

W1_d_write = AMPP_FUNCTION(CLK, E1_d_write_nxt, D1_data_out);


--E1_W_alu_result[21] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[21]
--operation mode is normal

E1_W_alu_result[21] = AMPP_FUNCTION(CLK, E1L041, E1L601, E1_E_shift_rot_result[21], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--S1_cpu_0_data_master_requests_cfi_flash_s1 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_s1
--operation mode is normal

S1_cpu_0_data_master_requests_cfi_flash_s1 = !E1_W_alu_result[21] & E1_d_read # W1_d_write;


--S1L12 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_s1~58
--operation mode is normal

S1L12 = S1L02 & !S1_cpu_0_data_master_requests_cfi_flash_s1 # !S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 # !S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable;


--S1_tri_state_bridge_0_avalon_slave_arb_addend[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1]
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_arb_addend[1]_lut_out = S1L001 & S1L201 # !S1L001 & S1L79;
S1_tri_state_bridge_0_avalon_slave_arb_addend[1] = DFFEAS(S1_tri_state_bridge_0_avalon_slave_arb_addend[1]_lut_out, CLK, D1_data_out, , S1L66, , , , );


--S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1]
--operation mode is normal

S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1]_lut_out = S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0];
S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1] = DFFEAS(S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1]_lut_out, CLK, D1_data_out, , , , , , );


--S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0]
--operation mode is normal

S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0]_lut_out = E1_d_read & S1L201 & !S1L99;
S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0] = DFFEAS(S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0]_lut_out, CLK, D1_data_out, , , , , , );


--S1L31 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_s1~134
--operation mode is normal

S1L31 = S1_cpu_0_data_master_requests_cfi_flash_s1 & !S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1] & !S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0] # !E1_d_read;


--S1L52 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_requests_cfi_flash_s1~178
--operation mode is normal