📄 for_ht3.ptf
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SYSTEM FOR_HT3
{
System_Wizard_Version = "4.20";
System_Wizard_Build = "178";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONE";
clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "0";
do_build_sim = "0";
board_class = "HT3";
CLOCKS
{
clk = "50000000";
}
hdl_language = "verilog";
view_master_priorities = "0";
name_column_width = "204";
desc_column_width = "205";
bustype_column_width = "0";
base_column_width = "75";
clock_column_width = "77";
end_column_width = "75";
device_family_id = "CYCLONE";
view_master_columns = "1";
BOARD_INFO
{
CONFIGURATION safe
{
length = "";
menu_position = "2";
offset = "0x00060000";
reference_designator = "U5";
}
CONFIGURATION user
{
length = "";
menu_position = "1";
offset = "0x00000000";
reference_designator = "U5";
}
JTAG_device_index = "1";
REFDES U5
{
base = "0x00200000";
}
REFDES U8
{
base = "0x00060000";
}
altera_avalon_cfi_flash
{
reference_designators = "U5";
}
altera_avalon_epcs_flash_controller
{
reference_designators = "U8";
}
class = "HT3";
class_version = "1.0";
device_family = "CYCLONE";
quartus_pgm_file = "system/HT3.sof";
quartus_project_file = "system/HT3.qpf";
reference_designators = "U8,U5";
sopc_system_file = "system/HT3.ptf";
}
view_frame_window = "115:108:921:648";
do_log_history = "0";
}
MODULE cpu_0
{
class = "altera_nios2";
class_version = "1.1";
iss_model_name = "altera_nios2";
HDL_INFO
{
PLI_Files = "";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu_0.v";
Synthesis_Only_Files = "";
}
MASTER instruction_master
{
PORT_WIRING
{
PORT i_address
{
direction = "output";
type = "address";
width = "22";
}
PORT i_read
{
direction = "output";
type = "read";
width = "1";
}
PORT i_readdata
{
direction = "input";
type = "readdata";
width = "32";
}
PORT i_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
Is_Enabled = "1";
}
}
MASTER data_master
{
PORT_WIRING
{
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT d_address
{
direction = "output";
type = "address";
width = "22";
}
PORT d_byteenable
{
direction = "output";
type = "byteenable";
width = "4";
}
PORT d_irq
{
direction = "input";
type = "irq";
width = "32";
}
PORT d_read
{
direction = "output";
type = "read";
width = "1";
}
PORT d_readdata
{
direction = "input";
type = "readdata";
width = "32";
}
PORT d_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
}
PORT d_write
{
direction = "output";
type = "write";
width = "1";
}
PORT d_writedata
{
direction = "output";
type = "writedata";
width = "32";
}
PORT jtag_debug_module_debugaccess_to_roms
{
direction = "output";
type = "debugaccess";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-31";
Is_Enabled = "1";
}
}
MASTER data_master2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
}
}
MASTER tightly_coupled_data_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER custom_instruction_master
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
Is_Custom_Instruction = "0";
Is_Enabled = "0";
}
}
SLAVE jtag_debug_module
{
PORT_WIRING
{
PORT jtag_debug_module_address
{
direction = "input";
type = "address";
width = "9";
}
PORT jtag_debug_module_begintransfer
{
direction = "input";
type = "begintransfer";
width = "1";
}
PORT jtag_debug_module_byteenable
{
direction = "input";
type = "byteenable";
width = "4";
}
PORT jtag_debug_module_clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT jtag_debug_module_debugaccess
{
direction = "input";
type = "debugaccess";
width = "1";
}
PORT jtag_debug_module_readdata
{
direction = "output";
type = "readdata";
width = "32";
}
PORT jtag_debug_module_reset
{
direction = "input";
type = "reset";
width = "1";
}
PORT jtag_debug_module_resetrequest
{
direction = "output";
type = "resetrequest";
width = "1";
}
PORT jtag_debug_module_select
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT jtag_debug_module_write
{
direction = "input";
type = "write";
width = "1";
}
PORT jtag_debug_module_writedata
{
direction = "input";
type = "writedata";
width = "32";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Read_Wait_States = "1";
Write_Wait_States = "1";
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Address_Width = "9";
Accepts_Internal_Connections = "1";
Requires_Internal_Connections = "instruction_master,data_master";
Accepts_External_Connections = "0";
Is_Enabled = "1";
Address_Alignment = "dynamic";
Base_Address = "0x00201000";
Is_Memory_Device = "1";
Is_Printable_Device = "0";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
JTAG_Hub_Base_Id = "593990";
JTAG_Hub_Instance_Id = "0";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
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