flash3.fit.eqn

EP1C6Q240C8的examples flash测试程序

--operation mode is normal

E1L163 = AMPP_FUNCTION(E1_R_ctrl_break, E1_R_ctrl_exception, E1_R_ctrl_uncond_cti, E1L063);


--E1_W_valid is FOR_HT3:inst|cpu_0:the_cpu_0|W_valid at LC_X27_Y10_N0
--operation mode is normal

E1_W_valid = AMPP_FUNCTION(CLK, E1L762, E1_E_valid, D1_data_out);


--H1_cpu_0_jtag_debug_module_arb_addend[1] is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[1] at LC_X14_Y12_N5
--operation mode is normal

H1_cpu_0_jtag_debug_module_arb_addend[1]_lut_out = H1L12 & H1L32 # !H1L12 & H1L22 # H1_cpu_0_jtag_debug_module_saved_chosen_master_vector[0] & !H1L32;
H1_cpu_0_jtag_debug_module_arb_addend[1] = DFFEAS(H1_cpu_0_jtag_debug_module_arb_addend[1]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , H1L72, , , , );


--P1L7 is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_requests_onchip_memory_0_s1~295 at LC_X15_Y12_N4
--operation mode is normal

P1L7 = !E1_F_pc[18] & !E1_F_pc[17] & !E1_i_read & !E1_F_pc[19];


--P1L8 is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_requests_onchip_memory_0_s1~296 at LC_X14_Y11_N4
--operation mode is normal

P1L8 = !E1_F_pc[13] & !E1_F_pc[16] & !E1_F_pc[15] & !E1_F_pc[14];


--P1L9 is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_requests_onchip_memory_0_s1~297 at LC_X15_Y12_N5
--operation mode is normal

P1L9 = P1L8 & !E1_F_pc[12] & !E1_F_pc[11] & P1L7;


--H1L3 is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~237 at LC_X15_Y12_N3
--operation mode is normal

H1L3 = P1L9 & E1_F_pc[10] & !E1_F_pc[9];


--H1_cpu_0_jtag_debug_module_arb_addend[0] is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0] at LC_X14_Y12_N3
--operation mode is normal

H1_cpu_0_jtag_debug_module_arb_addend[0]_lut_out = H1L12 & !H1L22 # !H1L12 & H1L22 # !H1L32 & H1_cpu_0_jtag_debug_module_saved_chosen_master_vector[0];
H1_cpu_0_jtag_debug_module_arb_addend[0] = DFFEAS(H1_cpu_0_jtag_debug_module_arb_addend[0]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , H1L72, , , , );


--J1L05 is FOR_HT3:inst|jtag_uart:the_jtag_uart|av_waitrequest~0 at LC_X13_Y12_N8
--operation mode is normal

J1L05 = E1_d_read # W1_d_write;


--H1_cpu_0_data_master_requests_cpu_0_jtag_debug_module is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_data_master_requests_cpu_0_jtag_debug_module at LC_X14_Y12_N2
--operation mode is normal

H1_cpu_0_data_master_requests_cpu_0_jtag_debug_module = R1L3 & !E1_W_alu_result[11] & E1_W_alu_result[12] & J1L05;


--H1L1 is FOR_HT3:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|add~349 at LC_X14_Y12_N6
--operation mode is normal

H1L1 = H1_cpu_0_data_master_requests_cpu_0_jtag_debug_module & !H1L3 & !H1_cpu_0_jtag_debug_module_arb_addend[0] & H1_cpu_0_jtag_debug_module_arb_addend[1] # !H1_cpu_0_data_master_requests_cpu_0_jtag_debug_module & H1_cpu_0_jtag_debug_module_arb_addend[1] # !H1L3 & !H1_cpu_0_jtag_debug_module_arb_addend[0];


--G1L11 is FOR_HT3:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~44 at LC_X14_Y12_N7
--operation mode is normal

G1L11 = H1_d1_reasons_to_wait & H1L1 # !H1_cpu_0_jtag_debug_module_arb_addend[0] # !H1L3;


--G1L21 is FOR_HT3:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~45 at LC_X14_Y8_N7
--operation mode is normal

G1L21 = E1_i_read # G1_cpu_0_instruction_master_dbs_address[1] & S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1] # !E1_F_pc[19];


--P1L5 is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_qualified_request_onchip_memory_0_s1~22 at LC_X15_Y12_N1
--operation mode is normal

P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register_qfbk = P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register;
P1L5 = P1L9 & !E1_F_pc[10] & E1_i_read # !P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register_qfbk;

--P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register is FOR_HT3:inst|onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1|cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register at LC_X15_Y12_N1
--operation mode is normal

P1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register = DFFEAS(P1L5, GLOBAL(CLK), GLOBAL(D1_data_out), , , P1L32, , , VCC);


--G1L31 is FOR_HT3:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~46 at LC_X14_Y8_N0
--operation mode is normal

G1L31 = !P1L5 & G1L11 & G1L21 & !S1L12;


--S1_cfi_flash_s1_wait_counter[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_wait_counter[0] at LC_X14_Y4_N6
--operation mode is normal

S1_cfi_flash_s1_wait_counter[0]_lut_out = !S1_cfi_flash_s1_wait_counter[0] & S1L3;
S1_cfi_flash_s1_wait_counter[0] = DFFEAS(S1_cfi_flash_s1_wait_counter[0]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , , , , , );


--S1L99 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|reduce_nor~2 at LC_X14_Y4_N9
--operation mode is normal

S1L99 = S1_cfi_flash_s1_wait_counter[0] # S1_cfi_flash_s1_wait_counter[3] # S1_cfi_flash_s1_wait_counter[1] # S1_cfi_flash_s1_wait_counter[2];


--S1L051 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~21 at LC_X12_Y6_N5
--operation mode is normal

S1L051 = S1L99 # !S1_d1_reasons_to_wait & S1L12 # S1L51;


--S1L251 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_firsttransfer~84 at LC_X14_Y4_N1
--operation mode is normal

S1L251 = S1_cpu_0_data_master_requests_cfi_flash_s1 & S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 # S1L52 & S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 # !S1_cpu_0_data_master_requests_cfi_flash_s1 & S1L52 & S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1;


--S1L741 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[0]~31 at LC_X14_Y4_N8
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable_qfbk = S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable;
S1L741 = S1L351 & !S1L251 # !S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable_qfbk # !S1L351 & S1L6 & !S1L251 # !S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable_qfbk;

--S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable at LC_X14_Y4_N8
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable = DFFEAS(S1L741, GLOBAL(CLK), GLOBAL(D1_data_out), , S1L1, , , , );


--S1L151 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~22 at LC_X13_Y4_N8
--operation mode is normal

S1L151 = S1L941 & S1_cfi_flash_s1_in_a_write_cycle # S1_cfi_flash_s1_in_a_read_cycle # !S1L941 & S1L99 & S1_cfi_flash_s1_in_a_write_cycle # S1_cfi_flash_s1_in_a_read_cycle;

--S1_d1_reasons_to_wait is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait at LC_X13_Y4_N8
--operation mode is normal

S1_d1_reasons_to_wait = DFFEAS(S1L151, GLOBAL(CLK), GLOBAL(D1_data_out), , , , , , );


--S1L1 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|always3~15 at LC_X14_Y4_N7
--operation mode is normal

S1L1 = !S1L151 & S1L12 # S1L51;


--S1L49 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1~130 at LC_X14_Y4_N2
--operation mode is normal

S1L49 = S1L741 & S1L351 # !S1L741 & S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1];


--S1L59 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1~131 at LC_X13_Y4_N2
--operation mode is normal

S1L59 = S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable & S1L251 # !S1L941;


--E1_R_ctrl_ld is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_ld at LC_X27_Y10_N2
--operation mode is normal

E1_R_ctrl_ld = AMPP_FUNCTION(CLK, E1_D_iw[4], E1_D_iw[1], E1_D_iw[0], E1_D_iw[2], D1_data_out);


--E1_R_ctrl_st is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_st at LC_X11_Y5_N3
--operation mode is normal

E1_R_ctrl_st = AMPP_FUNCTION(CLK, E1_D_iw[1], E1_D_iw[0], D1_data_out);


--E1_d_write_nxt is FOR_HT3:inst|cpu_0:the_cpu_0|d_write_nxt at LC_X11_Y5_N4
--operation mode is normal

E1_d_write_nxt = AMPP_FUNCTION(E1_E_new_inst, W1_d_write, F1_cpu_0_data_master_waitrequest, E1_R_ctrl_st);


--E1_R_logic_op[1] is FOR_HT3:inst|cpu_0:the_cpu_0|R_logic_op[1] at LC_X10_Y12_N5
--operation mode is normal

E1_R_logic_op[1] = AMPP_FUNCTION(CLK, E1L3, E1L28, E1L4, E1L7, D1_data_out);


--E1_E_src2[21] is FOR_HT3:inst|cpu_0:the_cpu_0|E_src2[21] at LC_X11_Y7_N2
--operation mode is normal

E1_E_src2[21] = AMPP_FUNCTION(CLK, E1_R_src2_use_imm, E1_D_iw[21], E1_D_iw[11], Z1_q_b[21], D1_data_out, E1L993, E1_R_ctrl_hi_imm);


--E1_E_src1[21] is FOR_HT3:inst|cpu_0:the_cpu_0|E_src1[21] at LC_X13_Y9_N5
--operation mode is normal

E1_E_src1[21] = AMPP_FUNCTION(CLK, Z1_q_a[21], E1L793, E1L435, E1_D_iw[25], D1_data_out, E1L693);


--E1_R_logic_op[0] is FOR_HT3:inst|cpu_0:the_cpu_0|R_logic_op[0] at LC_X10_Y12_N2
--operation mode is normal

E1_R_logic_op[0] = AMPP_FUNCTION(CLK, E1L18, E1L4, E1L3, E1L7, D1_data_out);


--E1L041 is FOR_HT3:inst|cpu_0:the_cpu_0|E_logic_result[21]~8237 at LC_X9_Y9_N6
--operation mode is normal

E1L041 = AMPP_FUNCTION(E1_R_logic_op[0], E1_R_logic_op[1], E1_E_src2[21], E1_E_src1[21]);


--E1_E_shift_rot_result[21] is FOR_HT3:inst|cpu_0:the_cpu_0|E_shift_rot_result[21] at LC_X7_Y9_N4
--operation mode is normal

E1_E_shift_rot_result[21] = AMPP_FUNCTION(CLK, E1_E_shift_rot_result[22], E1_E_shift_rot_result[20], E1_E_src1[21], E1_R_ctrl_shift_rot_right, D1_data_out, E1_E_new_inst);


--E1_R_ctrl_dst_data_sel_logic_result is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_dst_data_sel_logic_result at LC_X9_Y13_N5
--operation mode is normal

E1_R_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(CLK, E1L53, E1_D_iw[11], E1L51, E1L39, D1_data_out);


--E1_R_ctrl_dst_data_sel_cmp is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_dst_data_sel_cmp at LC_X9_Y13_N9
--operation mode is normal

E1_R_ctrl_dst_data_sel_cmp = AMPP_FUNCTION(CLK, E1L31, E1L88, E1L41, E1L19, D1_data_out);


--E1_R_ctrl_rdctl_inst is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_rdctl_inst at LC_X9_Y11_N2
--operation mode is normal

E1_R_ctrl_rdctl_inst = AMPP_FUNCTION(CLK, E1L858, E1_D_iw[15], E1L29, E1_D_iw[16], D1_data_out);


--E1L001 is FOR_HT3:inst|cpu_0:the_cpu_0|E_alu_result~0 at LC_X9_Y11_N9
--operation mode is normal

E1L001 = AMPP_FUNCTION(E1_R_ctrl_rdctl_inst, E1_R_ctrl_dst_data_sel_cmp);


--E1_R_ctrl_shift_rot is FOR_HT3:inst|cpu_0:the_cpu_0|R_ctrl_shift_rot at LC_X8_Y13_N5
--operation mode is normal

E1_R_ctrl_shift_rot = AMPP_FUNCTION(CLK, E1_D_iw[12], E1L29, E1_D_iw[13], D1_data_out);


--S1L841 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_winner[0]~20 at LC_X13_Y4_N0
--operation mode is normal

S1L841 = S1L741 & S1L6 # !S1L741 & S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0];


--E1_D_iw[4] is FOR_HT3:inst|cpu_0:the_cpu_0|D_iw[4] at LC_X14_Y15_N9
--operation mode is normal

E1_D_iw[4] = AMPP_FUNCTION(CLK, H1L3, E1L772, V1L8, E1L45, D1_data_out, E1_F_valid);


--E1L535 is FOR_HT3:inst|cpu_0:the_cpu_0|add~947 at LC_X11_Y11_N4
--operation mode is arithmetic

E1L535 = AMPP_FUNCTION(E1_E_src2[0], E1_E_src1[0]);

--E1L635 is FOR_HT3:inst|cpu_0:the_cpu_0|add~947COUT at LC_X11_Y11_N4
--operation mode is arithmetic

E1L635 = AMPP_FUNCTION(E1_E_src2[0], E1_E_src1[0]);


--E1L526 is FOR_HT3:inst|cpu_0:the_cpu_0|add~980 at LC_X10_Y11_N4
--operation mode is arithmetic

E1L526 = AMPP_FUNCTION(E1_E_src1[0], E1_E_src2[0]);

--E1L626 is FOR_HT3:inst|cpu_0:the_cpu_0|add~980COUT at LC_X10_Y11_N4
--operation mode is arithmetic

E1L626 = AMPP_FUNCTION(E1_E_src1[0], E1_E_src2[0]);


--E1L201 is FOR_HT3:inst|cpu_0:the_cpu_0|E_arith_result[0]~148 at LC_X12_Y7_N8
--operation mode is normal

E1L201 = AMPP_FUNCTION(E1L535, E1_E_alu_sub, E1L526);


--E1_D_iw[3] is FOR_HT3:inst|cpu_0:the_cpu_0|D_iw[3] at LC_X11_Y13_N3
--operation mode is normal

E1_D_iw[3] = AMPP_FUNCTION(CLK, H1L3, E1L672, V1L7, E1L45, D1_data_out, E1_F_valid);


--E1L735 is FOR_HT3:inst|cpu_0:the_cpu_0|add~948 at LC_X11_Y11_N5
--operation mode is arithmetic

E1L735 = AMPP_FUNCTION(E1_E_src1[1], E1_E_src2[1], E1L635);

--E1L835 is FOR_HT3:inst|cpu_0:the_cpu_0|add~948COUT at LC_X11_Y11_N5