flash3.fit.eqn

EP1C6Q240C8的examples flash测试程序

--S1L001 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|reduce_nor~124 at LC_X12_Y15_N5
--operation mode is normal

S1L001 = E1_d_byteenable[1] # E1_d_byteenable[0];


--F1_cpu_0_data_master_dbs_address[1] is FOR_HT3:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1] at LC_X12_Y13_N6
--operation mode is normal

F1_cpu_0_data_master_dbs_address[1]_lut_out = !F1_cpu_0_data_master_dbs_address[1];
F1_cpu_0_data_master_dbs_address[1] = DFFEAS(F1_cpu_0_data_master_dbs_address[1]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , F1L4, , , , );


--E1_d_byteenable[3] is FOR_HT3:inst|cpu_0:the_cpu_0|d_byteenable[3] at LC_X12_Y15_N7
--operation mode is normal

E1_d_byteenable[3] = AMPP_FUNCTION(CLK, E1L201, E1_D_iw[4], E1L301, E1_D_iw[3], D1_data_out);


--E1_d_byteenable[2] is FOR_HT3:inst|cpu_0:the_cpu_0|d_byteenable[2] at LC_X12_Y15_N4
--operation mode is normal

E1_d_byteenable[2] = AMPP_FUNCTION(CLK, E1L201, E1_D_iw[4], E1L301, E1_D_iw[3], D1_data_out);


--S1L101 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|reduce_nor~125 at LC_X12_Y15_N6
--operation mode is normal

S1L101 = F1_cpu_0_data_master_dbs_address[1] & E1_d_byteenable[3] # E1_d_byteenable[2] # !F1_cpu_0_data_master_dbs_address[1] & S1L001;


--S1L51 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_s1~136 at LC_X12_Y4_N6
--operation mode is normal

F1_cpu_0_data_master_no_byte_enables_and_last_term_qfbk = F1_cpu_0_data_master_no_byte_enables_and_last_term;
S1L51 = S1L41 & !F1_cpu_0_data_master_no_byte_enables_and_last_term_qfbk & S1L101 # !W1_d_write;

--F1_cpu_0_data_master_no_byte_enables_and_last_term is FOR_HT3:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_no_byte_enables_and_last_term at LC_X12_Y4_N6
--operation mode is normal

F1_cpu_0_data_master_no_byte_enables_and_last_term = DFFEAS(S1L51, GLOBAL(CLK), GLOBAL(D1_data_out), , , F1_last_dbs_term_and_run, , , VCC);


--S1_tri_state_bridge_0_avalon_slave_arb_addend[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0] at LC_X13_Y4_N9
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_arb_addend[0]_lut_out = S1L151 & !S1L6 # !S1L151 & S1L741 & S1L6 # !S1L741 & S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0];
S1_tri_state_bridge_0_avalon_slave_arb_addend[0] = DFFEAS(S1_tri_state_bridge_0_avalon_slave_arb_addend[0]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , S1L79, , , , );


--S1L6 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_in_a_read_cycle~49 at LC_X12_Y4_N0
--operation mode is normal

S1L6 = S1L12 & !S1L51 & S1_tri_state_bridge_0_avalon_slave_arb_addend[1] # !S1_tri_state_bridge_0_avalon_slave_arb_addend[0];

--S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] at LC_X12_Y4_N0
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] = DFFEAS(S1L6, GLOBAL(CLK), GLOBAL(D1_data_out), , S1L741, , , , );


--S1L351 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~56 at LC_X12_Y4_N8
--operation mode is normal

S1L351 = S1L51 & S1_tri_state_bridge_0_avalon_slave_arb_addend[1] # !S1_tri_state_bridge_0_avalon_slave_arb_addend[0] & !S1L12;

--S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] at LC_X12_Y4_N8
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] = DFFEAS(S1L351, GLOBAL(CLK), GLOBAL(D1_data_out), , S1L741, , , , );


--S1_cfi_flash_s1_in_a_read_cycle is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_in_a_read_cycle at LC_X12_Y4_N9
--operation mode is normal

S1_cfi_flash_s1_in_a_read_cycle = S1L6 # E1_d_read & S1L351;


--S1_cfi_flash_s1_wait_counter[3] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_wait_counter[3] at LC_X14_Y4_N4
--operation mode is normal

S1_cfi_flash_s1_wait_counter[3]_lut_out = S1L4 # S1L941 & S1_cfi_flash_s1_in_a_read_cycle # S1_cfi_flash_s1_in_a_write_cycle;
S1_cfi_flash_s1_wait_counter[3] = DFFEAS(S1_cfi_flash_s1_wait_counter[3]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , , , , , );


--S1L941 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_begins_xfer~40 at LC_X13_Y4_N7
--operation mode is normal

S1L941 = !S1_d1_reasons_to_wait & S1L12 # S1L51;


--S1_cfi_flash_s1_in_a_write_cycle is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_in_a_write_cycle at LC_X13_Y4_N3
--operation mode is normal

S1_cfi_flash_s1_in_a_write_cycle = S1L351 & W1_d_write;


--S1_cfi_flash_s1_wait_counter[2] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_wait_counter[2] at LC_X14_Y4_N5
--operation mode is normal

S1_cfi_flash_s1_wait_counter[2]_lut_out = S1L3 & S1_cfi_flash_s1_wait_counter[2] $ (!S1_cfi_flash_s1_wait_counter[0] & !S1_cfi_flash_s1_wait_counter[1]);
S1_cfi_flash_s1_wait_counter[2] = DFFEAS(S1_cfi_flash_s1_wait_counter[2]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , , , , , );


--S1_cfi_flash_s1_wait_counter[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_s1_wait_counter[1] at LC_X14_Y3_N2
--operation mode is normal

S1_cfi_flash_s1_wait_counter[1]_lut_out = S1L941 & !S1_cfi_flash_s1_in_a_read_cycle & S1_cfi_flash_s1_in_a_write_cycle # S1L2 # !S1L941 & S1L2;
S1_cfi_flash_s1_wait_counter[1] = DFFEAS(S1_cfi_flash_s1_wait_counter[1]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , , , , , );


--S1L89 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash~106 at LC_X14_Y3_N9
--operation mode is normal

S1L89 = !S1_cfi_flash_s1_wait_counter[2] & !S1_cfi_flash_s1_wait_counter[1];


--S1L79 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_select_n_to_the_cfi_flash~0 at LC_X13_Y4_N6
--operation mode is normal

S1L79 = S1_tri_state_bridge_0_avalon_slave_arb_addend[0] & S1_tri_state_bridge_0_avalon_slave_arb_addend[1] & S1L12 # S1L51 # !S1_tri_state_bridge_0_avalon_slave_arb_addend[0] & S1L12 # S1L51;


--E1_W_alu_result[20] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[20] at LC_X9_Y12_N2
--operation mode is normal

E1_W_alu_result[20] = AMPP_FUNCTION(CLK, E1L753, E1L931, E1_E_shift_rot_result[20], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L753 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[18]~COMBOUT at LC_X14_Y10_N9
--operation mode is normal

E1L753 = AMPP_FUNCTION(E1L186, E1_E_alu_sub, E1L195);

--E1_F_pc[18] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[18] at LC_X14_Y10_N9
--operation mode is normal

E1_F_pc[18] = AMPP_FUNCTION(CLK, E1L186, E1_E_alu_sub, E1L135, E1L195, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[19] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[19] at LC_X10_Y12_N6
--operation mode is normal

E1_W_alu_result[19] = AMPP_FUNCTION(CLK, E1L553, E1_R_ctrl_dst_data_sel_logic_result, E1_E_shift_rot_result[19], E1L831, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L553 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[17]~COMBOUT at LC_X14_Y9_N7
--operation mode is normal

E1L553 = AMPP_FUNCTION(E1_E_alu_sub, E1L876, E1L885);

--E1_F_pc[17] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[17] at LC_X14_Y9_N7
--operation mode is normal

E1_F_pc[17] = AMPP_FUNCTION(CLK, E1_E_alu_sub, E1L876, E1L825, E1L885, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[18] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[18] at LC_X12_Y9_N8
--operation mode is normal

E1_W_alu_result[18] = AMPP_FUNCTION(CLK, E1L731, E1_R_ctrl_dst_data_sel_logic_result, E1_E_shift_rot_result[18], E1L353, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L353 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[16]~COMBOUT at LC_X14_Y11_N2
--operation mode is normal

E1L353 = AMPP_FUNCTION(E1L585, E1L576, E1_E_alu_sub);

--E1_F_pc[16] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[16] at LC_X14_Y11_N2
--operation mode is normal

E1_F_pc[16] = AMPP_FUNCTION(CLK, E1L585, E1L576, E1L525, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[17] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[17] at LC_X12_Y9_N2
--operation mode is normal

E1_W_alu_result[17] = AMPP_FUNCTION(CLK, E1L153, E1_R_ctrl_dst_data_sel_logic_result, E1_E_shift_rot_result[17], E1L631, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L153 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[15]~COMBOUT at LC_X14_Y9_N9
--operation mode is normal

E1L153 = AMPP_FUNCTION(E1L276, E1L285, E1_E_alu_sub);

--E1_F_pc[15] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[15] at LC_X14_Y9_N9
--operation mode is normal

E1_F_pc[15] = AMPP_FUNCTION(CLK, E1L276, E1L285, E1L225, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[16] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[16] at LC_X11_Y12_N7
--operation mode is normal

E1_W_alu_result[16] = AMPP_FUNCTION(CLK, E1_R_ctrl_dst_data_sel_logic_result, E1L531, E1_E_shift_rot_result[16], E1L943, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L943 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[14]~COMBOUT at LC_X14_Y11_N3
--operation mode is normal

E1L943 = AMPP_FUNCTION(E1L966, E1L975, E1_E_alu_sub);

--E1_F_pc[14] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[14] at LC_X14_Y11_N3
--operation mode is normal

E1_F_pc[14] = AMPP_FUNCTION(CLK, E1L966, E1L975, E1L025, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[15] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[15] at LC_X11_Y12_N9
--operation mode is normal

E1_W_alu_result[15] = AMPP_FUNCTION(CLK, E1_R_ctrl_dst_data_sel_logic_result, E1L431, E1_E_shift_rot_result[15], E1L743, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L743 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[13]~COMBOUT at LC_X14_Y11_N7
--operation mode is normal

E1L743 = AMPP_FUNCTION(E1L775, E1L766, E1_E_alu_sub);

--E1_F_pc[13] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[13] at LC_X14_Y11_N7
--operation mode is normal

E1_F_pc[13] = AMPP_FUNCTION(CLK, E1L775, E1L766, E1L715, E1_E_alu_sub, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[14] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[14] at LC_X11_Y12_N2
--operation mode is normal

E1_W_alu_result[14] = AMPP_FUNCTION(CLK, E1_R_ctrl_dst_data_sel_logic_result, E1L331, E1_E_shift_rot_result[14], E1L543, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L543 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[12]~COMBOUT at LC_X10_Y13_N2
--operation mode is normal

E1L543 = AMPP_FUNCTION(E1L466, E1_E_alu_sub, E1L475);

--E1_F_pc[12] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[12] at LC_X10_Y13_N2
--operation mode is normal

E1_F_pc[12] = AMPP_FUNCTION(CLK, E1L466, E1_E_alu_sub, E1L415, E1L475, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[13] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[13] at LC_X9_Y12_N4
--operation mode is normal

E1_W_alu_result[13] = AMPP_FUNCTION(CLK, E1_R_ctrl_dst_data_sel_logic_result, E1L343, E1_E_shift_rot_result[13], E1L231, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L343 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[11]~COMBOUT at LC_X10_Y14_N2
--operation mode is normal

E1L343 = AMPP_FUNCTION(E1_E_alu_sub, E1L175, E1L166);

--E1_F_pc[11] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[11] at LC_X10_Y14_N2
--operation mode is normal

E1_F_pc[11] = AMPP_FUNCTION(CLK, E1_E_alu_sub, E1L175, E1L115, E1L166, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[12] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[12] at LC_X13_Y13_N5
--operation mode is normal

E1_W_alu_result[12] = AMPP_FUNCTION(CLK, E1L501, E1_R_ctrl_dst_data_sel_logic_result, E1_E_shift_rot_result[12], E1L131, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1_F_pc[10] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[10] at LC_X15_Y12_N8
--operation mode is normal

E1_F_pc[10] = AMPP_FUNCTION(CLK, E1L953, E1_R_ctrl_break, E1_R_ctrl_exception, D1_data_out, E1_W_valid);


--E1_W_alu_result[11] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[11] at LC_X13_Y13_N4
--operation mode is normal

E1_W_alu_result[11] = AMPP_FUNCTION(CLK, E1L043, E1_R_ctrl_dst_data_sel_logic_result, E1_E_shift_rot_result[11], E1L031, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L043 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[9]~COMBOUT at LC_X12_Y12_N1
--operation mode is normal

E1L043 = AMPP_FUNCTION(E1_E_alu_sub, E1L565, E1L556);

--E1_F_pc[9] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[9] at LC_X12_Y12_N1
--operation mode is normal

E1_F_pc[9] = AMPP_FUNCTION(CLK, E1_E_alu_sub, E1L565, E1L605, E1L556, D1_data_out, E1L263, E1L163, E1_W_valid);


--E1_W_alu_result[10] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[10] at LC_X13_Y13_N2
--operation mode is normal

E1_W_alu_result[10] = AMPP_FUNCTION(CLK, E1L833, E1_R_ctrl_dst_data_sel_logic_result, E1_E_shift_rot_result[10], E1L921, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--E1L833 is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[8]~COMBOUT at LC_X12_Y12_N7
--operation mode is normal

E1L833 = AMPP_FUNCTION(E1L356, E1L365, E1_E_alu_sub);