flash3.fit.eqn

EP1C6Q240C8的examples flash测试程序

--S1L061 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn~COMB_OUT at LC_X14_Y3_N8
--operation mode is normal

S1L061 = !S1_cfi_flash_s1_wait_counter[3] & !S1L941 & S1_cfi_flash_s1_in_a_read_cycle;


--S1L261 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash~COMB_OUT at LC_X13_Y4_N1
--operation mode is normal

S1L261 = S1_cfi_flash_s1_in_a_write_cycle & !S1L941 & S1L89 $ !S1_cfi_flash_s1_wait_counter[3];


--S1L341 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[20]~COMB_OUT at LC_X9_Y12_N6
--operation mode is normal

S1L341 = S1L351 & E1_W_alu_result[20] # !S1L351 & E1_F_pc[18];


--S1L141 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[19]~COMB_OUT at LC_X14_Y9_N3
--operation mode is normal

S1L141 = S1L351 & E1_W_alu_result[19] # !S1L351 & E1_F_pc[17];


--S1L931 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[18]~COMB_OUT at LC_X12_Y9_N6
--operation mode is normal

S1L931 = S1L351 & E1_W_alu_result[18] # !S1L351 & E1_F_pc[16];


--S1L731 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[17]~COMB_OUT at LC_X14_Y9_N4
--operation mode is normal

S1L731 = S1L351 & E1_W_alu_result[17] # !S1L351 & E1_F_pc[15];


--S1L531 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[16]~COMB_OUT at LC_X5_Y13_N2
--operation mode is normal

S1L531 = S1L351 & E1_W_alu_result[16] # !S1L351 & E1_F_pc[14];


--S1L331 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[15]~COMB_OUT at LC_X11_Y12_N4
--operation mode is normal

S1L331 = S1L351 & E1_W_alu_result[15] # !S1L351 & E1_F_pc[13];


--S1L131 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[14]~COMB_OUT at LC_X10_Y13_N4
--operation mode is normal

S1L131 = S1L351 & E1_W_alu_result[14] # !S1L351 & E1_F_pc[12];


--S1L921 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[13]~COMB_OUT at LC_X9_Y12_N5
--operation mode is normal

S1L921 = S1L351 & E1_W_alu_result[13] # !S1L351 & E1_F_pc[11];


--S1L721 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[12]~COMB_OUT at LC_X4_Y9_N2
--operation mode is normal

S1L721 = S1L351 & E1_W_alu_result[12] # !S1L351 & E1_F_pc[10];


--S1L521 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[11]~COMB_OUT at LC_X12_Y12_N2
--operation mode is normal

S1L521 = S1L351 & E1_W_alu_result[11] # !S1L351 & E1_F_pc[9];


--S1L321 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[10]~COMB_OUT at LC_X12_Y12_N5
--operation mode is normal

S1L321 = S1L351 & E1_W_alu_result[10] # !S1L351 & E1_F_pc[8];


--S1L121 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[9]~COMB_OUT at LC_X13_Y13_N8
--operation mode is normal

S1L121 = S1L351 & E1_W_alu_result[9] # !S1L351 & E1_F_pc[7];


--S1L911 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[8]~COMB_OUT at LC_X14_Y8_N2
--operation mode is normal

S1L911 = S1L351 & E1_W_alu_result[8] # !S1L351 & E1_F_pc[6];


--S1L711 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7]~COMB_OUT at LC_X6_Y13_N2
--operation mode is normal

S1L711 = S1L351 & E1_W_alu_result[7] # !S1L351 & E1_F_pc[5];


--S1L511 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[6]~COMB_OUT at LC_X14_Y11_N8
--operation mode is normal

S1L511 = S1L351 & E1_W_alu_result[6] # !S1L351 & E1_F_pc[4];


--S1L311 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[5]~COMB_OUT at LC_X14_Y10_N0
--operation mode is normal

S1L311 = S1L351 & E1_W_alu_result[5] # !S1L351 & E1_F_pc[3];


--S1L111 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[4]~COMB_OUT at LC_X14_Y9_N1
--operation mode is normal

S1L111 = S1L351 & E1_W_alu_result[4] # !S1L351 & E1_F_pc[2];


--S1L901 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[3]~COMB_OUT at LC_X14_Y10_N1
--operation mode is normal

S1L901 = S1L351 & E1_W_alu_result[3] # !S1L351 & E1_F_pc[1];


--S1L701 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[2]~COMB_OUT at LC_X12_Y12_N4
--operation mode is normal

S1L701 = S1L351 & E1_W_alu_result[2] # !S1L351 & E1_F_pc[0];


--S1L501 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[1]~COMB_OUT at LC_X12_Y13_N8
--operation mode is normal

S1L501 = S1L351 & F1_cpu_0_data_master_dbs_address[1] # !S1L351 & G1_cpu_0_instruction_master_dbs_address[1];


--L1_data_out[2] is FOR_HT3:inst|led_pio:the_led_pio|data_out[2] at LC_X16_Y6_N6
--operation mode is normal

L1_data_out[2]_lut_out = E1_d_writedata[2];
L1_data_out[2] = DFFEAS(L1_data_out[2]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , L1L1, , , , );


--L1_data_out[1] is FOR_HT3:inst|led_pio:the_led_pio|data_out[1] at LC_X16_Y6_N3
--operation mode is normal

L1_data_out[1]_lut_out = E1_d_writedata[1];
L1_data_out[1] = DFFEAS(L1_data_out[1]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , L1L1, , , , );


--L1_data_out[0] is FOR_HT3:inst|led_pio:the_led_pio|data_out[0] at LC_X16_Y6_N7
--operation mode is normal

L1_data_out[0]_lut_out = GND;
L1_data_out[0] = DFFEAS(L1_data_out[0]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , L1L1, E1_d_writedata[0], , , VCC);


--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y10_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y10_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y10_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y10_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L4 is altera_internal_jtag~SHIFTUSER at JTAG_X1_Y10_N1
A1L4 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L8 is altera_internal_jtag~UPDATEUSER at JTAG_X1_Y10_N1
A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);

--A1L3 is altera_internal_jtag~RUNIDLEUSER at JTAG_X1_Y10_N1
A1L3 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1L61Q);


--E1_F_pc[19] is FOR_HT3:inst|cpu_0:the_cpu_0|F_pc[19] at LC_X15_Y12_N0
--operation mode is normal

E1_F_pc[19] = AMPP_FUNCTION(CLK, E1L163, E1L601, E1L435, E1L263, D1_data_out, E1_W_valid);


--E1_i_read is FOR_HT3:inst|cpu_0:the_cpu_0|i_read at LC_X15_Y12_N2
--operation mode is normal

E1_i_read = AMPP_FUNCTION(CLK, E1_i_read, G1L31, E1_W_valid, D1_data_out);


--S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0] at LC_X12_Y6_N4
--operation mode is normal

S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0]_lut_out = S1L6 & !S1L051;
S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0] = DFFEAS(S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , , , , , );


--S1L02 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_s1~57 at LC_X15_Y12_N9
--operation mode is normal

S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1]_qfbk = S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1];
S1L02 = !E1_i_read & !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0] & !S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1]_qfbk & E1_F_pc[19];

--S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1] at LC_X15_Y12_N9
--operation mode is normal

S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[1] = DFFEAS(S1L02, GLOBAL(CLK), GLOBAL(D1_data_out), , , S1_cpu_0_instruction_master_read_data_valid_cfi_flash_s1_shift_register[0], , , VCC);


--S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 at LC_X14_Y4_N0
--operation mode is normal

S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1_lut_out = S1_cpu_0_data_master_requests_cfi_flash_s1 & S1L49 # S1L59 & S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1;
S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1 = DFFEAS(S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , , , , , );


--E1_d_read is FOR_HT3:inst|cpu_0:the_cpu_0|d_read at LC_X13_Y12_N4
--operation mode is normal

E1_d_read = AMPP_FUNCTION(CLK, F1_cpu_0_data_master_waitrequest, E1_d_read, E1_E_new_inst, E1_R_ctrl_ld, D1_data_out);


--E1_W_alu_result[21] is FOR_HT3:inst|cpu_0:the_cpu_0|W_alu_result[21] at LC_X12_Y9_N5
--operation mode is normal

E1_W_alu_result[21] = AMPP_FUNCTION(CLK, E1L601, E1L041, E1_E_shift_rot_result[21], E1_R_ctrl_dst_data_sel_logic_result, D1_data_out, E1L001, E1_R_ctrl_shift_rot);


--S1_cpu_0_data_master_requests_cfi_flash_s1 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_s1 at LC_X12_Y4_N4
--operation mode is normal

W1_d_write_qfbk = W1_d_write;
S1_cpu_0_data_master_requests_cfi_flash_s1 = !E1_W_alu_result[21] & E1_d_read # W1_d_write_qfbk;

--W1_d_write is FOR_HT3:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|d_write at LC_X12_Y4_N4
--operation mode is normal

W1_d_write = AMPP_FUNCTION(CLK, E1_d_write_nxt, D1_data_out, GND);


--S1L12 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_s1~58 at LC_X12_Y4_N7
--operation mode is normal

S1L12 = S1L02 & !S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable # !S1_cpu_0_data_master_requests_cfi_flash_s1 # !S1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_s1;


--S1_tri_state_bridge_0_avalon_slave_arb_addend[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1] at LC_X13_Y4_N4
--operation mode is normal

S1_tri_state_bridge_0_avalon_slave_arb_addend[1]_lut_out = S1L151 & S1L351 # !S1L151 & S1L841;
S1_tri_state_bridge_0_avalon_slave_arb_addend[1] = DFFEAS(S1_tri_state_bridge_0_avalon_slave_arb_addend[1]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , S1L79, , , , );


--S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0] at LC_X12_Y6_N7
--operation mode is normal

S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0]_lut_out = !S1L051 & E1_d_read & S1L351;
S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0] = DFFEAS(S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0]_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , , , , , );


--S1L31 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_s1~134 at LC_X12_Y4_N3
--operation mode is normal

S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1]_qfbk = S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1];
S1L31 = S1_cpu_0_data_master_requests_cfi_flash_s1 & !S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1]_qfbk & !S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0] # !E1_d_read;

--S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1] is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1] at LC_X12_Y4_N3
--operation mode is normal

S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[1] = DFFEAS(S1L31, GLOBAL(CLK), GLOBAL(D1_data_out), , , S1_cpu_0_data_master_read_data_valid_cfi_flash_s1_shift_register[0], , , VCC);


--S1L52 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_requests_cfi_flash_s1~178 at LC_X15_Y12_N7
--operation mode is normal

S1L52 = !E1_i_read & E1_F_pc[19];


--S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 at LC_X13_Y4_N5
--operation mode is normal

S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1_lut_out = S1L52 & S1L841 # S1L59 & S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1;
S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 = DFFEAS(S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1_lut_out, GLOBAL(CLK), GLOBAL(D1_data_out), , , , , , );


--S1L41 is FOR_HT3:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_s1~135 at LC_X12_Y4_N5
--operation mode is normal

S1L41 = S1L31 & !S1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_s1 # !S1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable # !S1L52;


--E1_d_byteenable[1] is FOR_HT3:inst|cpu_0:the_cpu_0|d_byteenable[1] at LC_X12_Y15_N3
--operation mode is normal

E1_d_byteenable[1] = AMPP_FUNCTION(CLK, E1L201, E1_D_iw[4], E1L301, E1_D_iw[3], D1_data_out);


--E1_d_byteenable[0] is FOR_HT3:inst|cpu_0:the_cpu_0|d_byteenable[0] at LC_X12_Y15_N0
--operation mode is normal

E1_d_byteenable[0] = AMPP_FUNCTION(CLK, E1L201, E1_D_iw[4], E1L301, E1_D_iw[3], D1_data_out);