clock.v

用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!

// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2006-2009 (c) Lpstar Corporation
// ALL RIGHTS RESERVED
// This core is licensed under the Lpstar Open IP Core Agreement version 1.0 and 
// subsequent versions
//
// Lpstar Corporation    								TEL : [phone] (China)
//										                  Web  : http://www.lpstar.com/
// China                                Email: [e-mail]
// =============================================================================
//                         FILE DETAILS
// Project          : clock
// File             : clock.v
// Title            :
// Dependencies     : 
// Description      : This module is top level for clock.    
// =============================================================================
//                        REVISION HISTORY
// Version          : 1.0
// Author(s)        : Red.fount
// Mod. Date        : Oct. 09, 2007
// Changes Made     : Initial Creation
// =============================================================================

`include	"led_display.v"
module clock(
					 	 CLOCK,
					 	 BUT,
					 	 NUMLED_SIG,
					 	 NUMLED_GND,
					 	 );
input							CLOCK;		//8.192MHz;
input			[3:0]		BUT;
output		[7:0]		NUMLED_SIG;
output		[3:0]		NUMLED_GND;



reg				[31:0]	counter;
reg				[7:0]		delay_1s;
reg								delay_1h;
reg				[3:0]		minute_L;
reg				[7:0]		minute_H;
reg				[3:0]		hour_L;
reg				[7:0]		hour_H;
reg				[7:0]		hour;
reg				[7:0]		coun_s;
reg				[7:0]		coun_m;
reg				[7:0]		coun_h;
reg				[3:0]		state;
reg				[7:0]		counter1;




wire							rst;
wire							set;
wire							model;
wire							adder;

reg								clear;




always @(posedge CLOCK)
	begin
		if(!BUT[0])
			begin
				counter <= 8'h00000000;
			end
		else
			begin
				counter <= counter + 1'b1;
			end
	end

always @(posedge counter[12])//0.001s   counter[22]
	begin
		if(!BUT[0])
			begin
				delay_1s <= 8'b00000000;
				minute_H <= 4'b0000;
				minute_L <= 4'b0000;
				hour_L <= 4'b0000;
				hour_L <= 4'b0000;
			end
		else
			begin
				if	(delay_1s == 'h3B)
					begin
						delay_1s <= 'b00000000;
						//////////////////////
						if (minute_L == 'h9)
							begin
								minute_L <= 'b0000;
								if	(minute_H == 'h5)
									begin
										minute_H <= 'h0;
										if (hour_L == 'h9)
											begin
												hour_L <= 'b0000;
												hour_H <= hour_H + 'b1;
											end
										else
											begin
												if	({hour_H,hour_L}	== 'h23)//display 24 hour
													begin
														hour_L <= 'b0000;
														hour_H <= 'b0000;
													end
												else
													begin
														hour_L <= hour_L + 'b1;
													end
											end
									end
								else
									begin
										minute_H <= minute_H + 'b1;
									end
							end
						else
							begin
								minute_L <= minute_L + 'b1;
							end
						
						/////////////////////
					end
				else
					begin
						delay_1s <= delay_1s + 'b1;
					end
			end
	end






led_display		led_display(
									 				.RST(BUT[0]),
									 				.CLOCK(CLOCK),
									 				.DELAY(counter[10]),
									 				.POINT(counter[22]),
									 				.LED_GND(NUMLED_GND),
									 				.LED_SIG(NUMLED_SIG),
									 				.LED0_REG(hour_H),
									 				.LED1_REG(hour_L),
									 				.LED2_REG(minute_H),
									 				.LED3_REG(minute_L)
									 				);
endmodule