led_display.v

用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!

module	led_display	(
									 RST,
									 CLOCK,
									 DELAY,
									 POINT,
									 LED_GND,
									 LED_SIG,
									 LED0_REG,
									 LED1_REG,
									 LED2_REG,
									 LED3_REG,
									 );
input							RST;
input							CLOCK;
input							DELAY;
input							POINT;
input			[3:0]		LED0_REG;
input			[3:0]		LED1_REG;
input			[3:0]		LED2_REG;
input			[3:0]		LED3_REG;
output		[3:0]		LED_GND;
output		[7:0]		LED_SIG;

reg				[7:0]		LED_GND;
reg				[7:0]		counter;
reg				[3:0]		state;
reg				[3:0]		led_sig_reg;
reg				[7:0]		LED_SIG;
reg				[3:0]		led_gnd_reg;
always @(posedge DELAY)
	begin
		if	(!RST)
			begin
				state <= 4'b0000;
				led_sig_reg <=8'b11011111;
				led_gnd_reg <= 4'b1111;
				counter <= 8'b00000000;
			end
		else
			begin
				counter <= counter + 1'b1;
				state <= state +'b1;
				case(state)
					4'h0:	begin
									led_gnd_reg <= 4'b0111;
									led_sig_reg <= LED0_REG;
								end

					4'h1:	begin
									led_gnd_reg <= 4'b1011;
									led_sig_reg <= LED1_REG;
								end

					4'h2:	begin
									led_gnd_reg <= 4'b1101;
									led_sig_reg <= LED2_REG;
								end

					4'h3:	begin
									led_gnd_reg <= 4'b1110;
									led_sig_reg <= LED3_REG;
								end
///调节亮度
					4'h4:	begin
									led_gnd_reg <= 4'b1011;
									led_sig_reg <= LED1_REG;
								end
					4'h5:	begin
									led_gnd_reg <= 4'b1101;
									led_sig_reg <= LED2_REG;
								end
					default: state <= 4'b0000;
				endcase
			end		
	end
always @(posedge CLOCK)
	begin
		if	(!RST)
			begin
				LED_GND <= 'b0000;
				LED_SIG <= 8'b11011111;
			end
		else
			begin
				if	(led_gnd_reg == 4'b1011)
					begin
						case(led_sig_reg)
							4'h0:	LED_SIG <= {2'b11,POINT,5'b10111};
							4'h1:	LED_SIG <= {2'b00,POINT,5'b10100};
							4'h2:	LED_SIG <= {2'b11,POINT,5'b01101};
							4'h3:	LED_SIG <= {2'b01,POINT,5'b11101};
							4'h4:	LED_SIG <= {2'b00,POINT,5'b11110};
							4'h5:	LED_SIG <= {2'b01,POINT,5'b11011};
							4'h6:	LED_SIG <= {2'b11,POINT,5'b11011};
							4'h7:	LED_SIG <= {2'b00,POINT,5'b10101};
							4'h8:	LED_SIG <= {2'b11,POINT,5'b11111};
							4'h9:	LED_SIG <= {2'b01,POINT,5'b11111};
							default:	LED_SIG <= {2'b11,POINT,5'b10111};
						endcase
						LED_GND <= led_gnd_reg;						
					end
				else
					begin
						case(led_sig_reg)
							4'h0:	LED_SIG <= 8'b11010111;
							4'h1:	LED_SIG <= 8'b00010100;
							4'h2:	LED_SIG <= 8'b11001101;
							4'h3:	LED_SIG <= 8'b01011101;
							4'h4:	LED_SIG <= 8'b00011110;
							4'h5:	LED_SIG <= 8'b01011011;
							4'h6:	LED_SIG <= 8'b11011011;
							4'h7:	LED_SIG <= 8'b00010101;
							4'h8:	LED_SIG <= 8'b11011111;
							4'h9:	LED_SIG <= 8'b01011111;
							default:	LED_SIG <= 8'b11010111;
						endcase
					LED_GND <= led_gnd_reg;
			end
		end
		
	end


endmodule