mcf548x-pne-insight.gdb

实现快速傅立叶变换算法,provides test framwork for FFT testing

#
# Processor initialization file for MCF5485 EVA board
# for use with gdb/insight and bdm-interface.
#
# Written by Aimo Suess <[e-mail]>
#

#############################################################################
#
# Function:     reg
#
# Description:  This function displays all register.
#
#
# Parameters:   none
#
# 
# Returns:      none
#
#
# State:        
#
#############################################################################

define reg

    info r

end

document reg

    List all register and their contents for selected stack frame.

end

#############################################################################
#
# Function:     delay
#
# Description:  This function delays the execution of serveral commands.
#
#
# Parameters:   none
#
# 
# Returns:      none
#
#
# State:        
#
#############################################################################

define delay

set $delcount = 0

while ($delcount < 2000)
  set $delcount += 1
end

end

#############################################################################
#
# Function:     TargetInit_MCF5485
#
# Description:  This function sets the CPU register to load code to ram.
#
#
# Parameters:   none
#
# 
# Returns:      none
#
#
# State:        
#
#############################################################################

define mcf548xevb_init

bdm-write-creg 0x801 0x00000000

#
# Set MBAR (CPU reg 0x0C0F) to 0x10000000
# set $mbar = 0x10000000
bdm-write-creg 0xC0F 0x80000000

#
# Set RAMBAR0 = 0x20000021
# RAMBAR0 is an absolute CPU register
# This is the location of the internal 4k of SRAM on the chip
#
# set $rambar = 0x20000021
bdm-write-creg 0xC04 0x20000021

#
# Set RAMBAR1 = 0x20001021
# RAMBAR1 is an absolute CPU register
# This is the location of the internal 4k of SRAM on the chip
#
# not supported set $rambar1 = 0x20001021
bdm-write-creg 0xC05 0x20001021

# -----------------------------------------------------------------------------


# -----------------------------------------------------------------------------
# FlexBus CS0 (FLASH)
# writemem.l 0x10000500 0xFE000000	; CSAR0	: base address 0xFE00_0000
#set base address for CS Address register 
set *(unsigned long  *)0x80000500 = 0xFE000000

# writemem.l 0x10000508 0x00001900	; CSCR0	: 
set *(unsigned long  *)0x80000508 = 0x00001900

# writemem.l 0x10000504 0x01FF0001	; CSMR0	: 32 MByte size
set *(unsigned long  *)0x80000504 = 0x01FF0001

# -----------------------------------------------------------------------------
# DDR SDRAM : CS0 - 0x0000_0000 .. 0x07FF_FFFF - 128MByte

# writemem.l 0x10000004 0x000002AA	; SDRAMDS : SSTL 2 Class 1
set *(unsigned long  *)0x80000004 = 0x000002AA

# writemem.l 0x10000020 0x0000001A	; CS0CFG : 128MByte
set *(unsigned long  *)0x80000020 = 0x0000001A

# writemem.l 0x10000024 0x00000000	; CS1CFG
#-ctset *(unsigned long  *)0x10000024 = 0x00000000

# writemem.l 0x10000028 0x00000000	; CS2CFG
#-ctset *(unsigned long  *)0x10000028 = 0x00000000

# writemem.l 0x1000002C 0x00000000	; CS3CFG
#-ctset *(unsigned long  *)0x1000002C = 0x00000000

# writemem.l 0x10000108 0x53722930	; SDCFG1
set *(unsigned long  *)0x80000108 = 0x53722930
#writemem.l 0x1000010C 0x24330000	; SDCFG2
set *(unsigned long  *)0x8000010C = 0x24330000

# writemem.l 0x10000104 0xE10F0002;   SDCR + IPALL
set *(unsigned long  *)0x80000104 = 0xE10F0002

# writemem.l 0x10000100 0x40010000;   SDMR (write to LEMR)
set *(unsigned long  *)0x80000100 = 0x40010000

# writemem.l 0x10000100 0x05890000;   SDRM (write to LMR)
set *(unsigned long  *)0x80000100 = 0x05890000

# writemem.l 0x10000104 0xE10F0002;   SDCR + IPALL
set *(unsigned long  *)0x80000104 = 0xE10F0002

# writemem.l 0x10000104 0xE10F0004;   SDCR + IREF (first refresh)
set *(unsigned long  *)0x80000104 = 0xE10F0004

# writemem.l 0x10000104 0xE10F0004;   SDCR + IREF (second refresh)
set *(unsigned long  *)0x80000104 = 0xE10F0004

# writemem.l 0x10000100 0x01890000;   SDMR (write to LMR)
set *(unsigned long  *)0x80000100 = 0x01890000

# writemem.l 0x10000104 0x710F0F00;   SDCR (lock SDMR and enable refresh)
set *(unsigned long  *)0x80000104 = 0x710F0F00


end

#############################################################################
#
# Function:     ExecutionScript
#
# Description:  Use the commands that have been defined in order to
#               initialize the target hardware for loading via bdm.
#
#
# Connect to the target.
#
#                                    (typically)
#  /dev/bdmcf0 --> I/O port: 0x0378 --> LPT1
#  /dev/bdmcf1 --> I/O port: 0x0278 --> LPT2
#  /dev/bdmcf2 --> I/O port: 0x03BC --> LPT3
#  /dev/bdmcf3 --> I/O port: 0x02BC --> LPT4
#
#  Uncomment one of the following lines as
#  appropriate for your configuration.
#
#
#############################################################################

define st

target bdm /dev/bdmcf0
bdm-wait
delay
mcf548xevb_init
#r

end