var_regs.h

实现快速傅立叶变换算法,provides test framwork for FFT testing

#ifndef CYGONCE_HAL_VAR_REGS_H
#define CYGONCE_HAL_VAR_REGS_H

//==========================================================================
//
//      var_regs.h
//
//      ColdFire MCF5484 variant CPU definitions
//
//==========================================================================
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//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Enrico Piria
// Contributors:
// Date:         2005-25-06
// Purpose:      Provide register definitions for the MCF5484.
// Description:
// Usage:        Included via "coldfire_regs.h". Do not use directly.
//
//####DESCRIPTIONEND####
//==========================================================================

// CPU space registers definitions

#define CYGARC_REG_CACR             0x002
#define CYGARC_REG_ACR0             0x004
#define CYGARC_REG_ACR1             0x005
#define CYGARC_REG_ACR2             0x006
#define CYGARC_REG_ACR3             0x007
#define CYGARC_REG_VBR              0x801
#define CYGARC_REG_ROMBAR0          0xC00
#define CYGARC_REG_RAMBAR0          0xC04
#define CYGARC_REG_MBAR             0xC0F

// ---------------------------------------------------------------------------

//--------------------------------------------------------------------------------
// MCF5484 specific CACR configuration macros
// Data Cache:
#define MCF5484_CACR_DCACHE_DEC               (0x01 << 31)  //Enable data cache
#define MCF5484_CACR_DCACHE_DW                (0x01 << 30)  //Data default write-protected
#define MCF5484_CACR_DCACHE_DESB              (0x01 << 29)  //Enable data store buffer
#define MCF5484_CACR_DCACHE_DDPI              (0x01 << 28)  //Disable CPUSHL invalidation. /Normal setting : 0/
#define MCF5484_CACR_DCACHE_DHLCK             (0x01 << 27)  //Half data cache lock. /Normal setting: 0/

#define MCF5484_CACR_DCACHE_DDCM(x)           (((x)& 0x03) << 25) //Default Data Cache Mode
#define MCF5484_CACR_DCACHE_DDCM_WRITE_THROUGH       (0x00)      // write-through, imprecise
#define MCF5484_CACR_DCACHE_DDCM_COPYBACK            (0x01)      // copyback
#define MCF5484_CACR_DCACHE_DDCM_INHIBITED_PRECISE   (0x02)      // cache-inhibite precise
#define MCF5484_CACR_DCACHE_DDCM_INHIBITED_IMPRECISE (0x03)      // cache-inhibite imprecise

#define MCF5484_CACR_DCACHE_DCINVA            (0x01 << 24)       //Data cache invalidate all /Note the caches are not cleared on power-up or normal reset/
#define MCF5484_CACR_DCACHE_DDSP              (0x01 << 23)       //Data default supervisor-protect
#define MCF5484_CACR_DCACHE_BEC               (0x01 << 19)       //Enable Branch Cache /0: Branch cache disabled. This may be useful if code is unlikely to be reused./
#define MCF5484_CACR_DCACHE_BCINVA            (0x01 << 18)       //Branch cache invalidate /Invalidation occurs when this bit is written as a 1. Note that branch caches are not cleared on power-up or normal reset./

// Instruction Cache:
#define MCF5484_CACR_ICACHE_IEC               (0x01 << 15)  //Enable instruction cache
#define MCF5484_CACR_ICACHE_DNFB              (0x01 << 13)  //Default cache-inhibited fill buffer
#define MCF5484_CACR_ICACHE_IDPI              (0x01 << 12)  //Instruction CPUSHL invalidate disable /Normal operation: 0/
#define MCF5484_CACR_ICACHE_IHLCK             (0x01 << 11)  //Instruction cache half-lock. /Normal operation: 0/
#define MCF5484_CACR_ICACHE_IDCM              (0x01 << 10)  //Instruction default cache mode. /0 Cacheable 1 Cache-inhibited/
#define MCF5484_CACR_ICACHE_ICINVA            (0x01 << 8)   //Instruction cache invalidate /Note the caches are not cleared on power-up or normal reset/
#define MCF5484_CACR_ICACHE_IDSP              (0x01 << 7)   //Default instruction supervisor protection bit.
#define MCF5484_CACR_ICACHE_EUSP              (0x01 << 5)   //Enable USP. Enables the use of the user stack pointer /0 USP disabled. Core uses a single stack pointer. 1 USP enabled. Core uses separate supervisor and user stack pointers./
#define MCF5484_CACR_ICACHE_DF                (0x01 << 4)   //Disable FPU. Determines whether the FPU is enabled /0 FPU enabled. 1 FPU disabled/

//--------------------------------------------------------------------------------

// End of var_regs.h
#endif // ifdef CYGONCE_HAL_VAR_REGS_H