var_cache.h

实现快速傅立叶变换算法,provides test framwork for FFT testing

// Unlock entire cache
#define HAL_DCACHE_UNLOCK_ALL()

// DCACHE API:
// NOTE: DISABLE_DCACHE() ENABLE_DCACHE() Must be used parallel.
//       And DISABLE_DCACHE() first, ENABLE_DCACHE() next
//       These two functions are used to disable data cache temperaly only if the dcache is used.
#define DISABLE_DCACHE()                                                       \
CYG_MACRO_START                                                                \
   HAL_DCACHE_IS_ENABLED(cyg_hal_sys_dcache_status);                       \
   if(cyg_hal_sys_dcache_status)                                           \
   {                                                                           \
       HAL_DCACHE_DISABLE();                                                   \
   }                                                                           \
CYG_MACRO_END

#define ENABLE_DCACHE()                                                        \
CYG_MACRO_START                                                                \
   if(cyg_hal_sys_dcache_status)                                           \
   {                                                                           \
       HAL_DCACHE_ENABLE();                                                    \
   }                                                                           \
CYG_MACRO_END

// ----------------------------------------------------------------------------
// Data cache line control

// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )

// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
#define HAL_DCACHE_FLUSH( _base_ , _size_ )


// Invalidate cache lines in the given range without writing to memory.
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )

// Write dirty cache lines to memory for the given address range.
#define HAL_DCACHE_STORE( _base_ , _size_ )

// Preread the given range into the cache with the intention of reading
// from it later.
#define HAL_DCACHE_READ_HINT( _base_ , _size_ )

// Preread the given range into the cache with the intention of writing
// to it later.
#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )

// Allocate and zero the cache lines associated with the given range.
#define HAL_DCACHE_ZERO( _base_ , _size_ )

// Set ACR0 register:
#define HAL_SET_ACR0(_reg_setting_)                                             \
CYG_MACRO_START                                                                                             \
   cyg_hal_current_acr[0] = _reg_setting_;                                         \
   CYGARC_MOVEC(_reg_setting_, CYGARC_REG_ACR0);                                                             \
CYG_MACRO_END

// Set ACR1 register:
#define HAL_SET_ACR1(_reg_setting_)                                             \
CYG_MACRO_START                                                                                             \
   cyg_hal_current_acr[1] = _reg_setting_;                                         \
   CYGARC_MOVEC(_reg_setting_, CYGARC_REG_ACR1);                                                             \
CYG_MACRO_END

// Set ACR2 register:
#define HAL_SET_ACR2(_reg_setting_)                                             \
CYG_MACRO_START                                                                                             \
   cyg_hal_current_acr[2] = _reg_setting_;                                         \
   CYGARC_MOVEC(_reg_setting_, CYGARC_REG_ACR2);                                                             \
CYG_MACRO_END

// Set ACR3 register:
#define HAL_SET_ACR3(_reg_setting_)                                             \
CYG_MACRO_START                                                                                             \
   cyg_hal_current_acr[3] = _reg_setting_;                                         \
   CYGARC_MOVEC(_reg_setting_, CYGARC_REG_ACR3);                                                             \
CYG_MACRO_END

// Query ACR0 states:
#define HAL_QUERY_ACR0(_ret_)                                             \
CYG_MACRO_START                                                         \
    _ret_ = cyg_hal_current_acr[0];                                         \
CYG_MACRO_END

// Query ACR1 states:
#define HAL_QUERY_ACR1(_ret_)                                             \
CYG_MACRO_START                                                         \
    _ret_ = cyg_hal_current_acr[1];                                         \
CYG_MACRO_END

// Query ACR2 states:
#define HAL_QUERY_ACR2(_ret_)                                             \
CYG_MACRO_START                                                         \
    _ret_ = cyg_hal_current_acr[2];                                         \
CYG_MACRO_END

// Query ACR3 states:
#define HAL_QUERY_ACR3(_ret_)                                             \
CYG_MACRO_START                                                         \
    _ret_ = cyg_hal_current_acr[3];                                         \
CYG_MACRO_END


// ----------------------------------------------------------------------------
// Global control of Instruction cache

// Enable the instruction cache
#define HAL_ICACHE_ENABLE()                                                    \
CYG_MACRO_START                                                                \
   cyg_uint32  _cacr_setval;                                                   \
   cyg_hal_current_cacr_setting.icache = (0x00 | MCF5484_CACR_ICACHE_IEC);             \
   _cacr_setval = (cyg_hal_current_cacr_setting.icache | cyg_hal_current_cacr_setting.dcache); \
   CYGARC_MOVEC(_cacr_setval, CYGARC_REG_CACR);                                \
   _cacr_setval = (cyg_uint32)MCF5484_DEVS;                                    \
   _cacr_setval |= 0xc040;                                                     \
   HAL_SET_ACR2(_cacr_setval);                                        \
CYG_MACRO_END

// Disable the instruction cache
#define HAL_ICACHE_DISABLE() \
CYG_MACRO_START                                                                \
   HAL_ICACHE_INVALIDATE_ALL();                                                \
   CACHE_REG_ICACHE_DISABLE();                                                 \
   HAL_SET_ACR2(0x00);                                        \
CYG_MACRO_END

#define CACHE_REG_ICACHE_DISABLE()   \
CYG_MACRO_START                                                                \
cyg_uint32  _cacr_setval;                                                      \
   cyg_hal_current_cacr_setting.icache =(0x00);                                \
   _cacr_setval = (cyg_hal_current_cacr_setting.icache | cyg_hal_current_cacr_setting.dcache); \
   CYGARC_MOVEC(_cacr_setval, CYGARC_REG_CACR);                                \
CYG_MACRO_END

// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL()                                            \
CYG_MACRO_START                                                                \
   cyg_uint32  _cacr_setval;                                                   \
   _cacr_setval = (cyg_hal_current_cacr_setting.icache | cyg_hal_current_cacr_setting.dcache   \
                                               | MCF5484_CACR_ICACHE_ICINVA);  \
   CYGARC_MOVEC(_cacr_setval, CYGARC_REG_CACR);                                \
CYG_MACRO_END

// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC()                                                      \
CYG_MACRO_START                                                                \
   cyg_uint32 _cacr_setval;                                                    \
   _cacr_setval = (cyg_hal_current_cacr_setting.icache | cyg_hal_current_cacr_setting.dcache   \
                                               | MCF5484_CACR_ICACHE_ICINVA);  \
   CYGARC_MOVEC(_cacr_setval, CYGARC_REG_CACR);                                \
CYG_MACRO_END
// Query the state of the instruction cache
#define HAL_ICACHE_IS_ENABLED(_state_)                                         \
CYG_MACRO_START                                                                \
        if (cyg_hal_current_cacr_setting.icache & MCF5484_CACR_ICACHE_IEC)     \
        {                                                                      \
            _state_ = 1;                                                       \
        }else                                                                  \
        {                                                                      \
            _state_ = 0;                                                       \
        }                                                                      \
CYG_MACRO_END

// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)


// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
#define HAL_ICACHE_LOCK(_base_, _size_)

// Undo a previous lock operation
#define HAL_ICACHE_UNLOCK(_base_, _size_)

// Unlock entire cache
#define HAL_ICACHE_UNLOCK_ALL()

// ----------------------------------------------------------------------------
// Instruction cache line control

// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )

// ---------------------------------------------------------------------------
// End of var_cache.h
#endif // ifndef CYGONCE_VAR_CACHE_H