var_cache.h

实现快速傅立叶变换算法,provides test framwork for FFT testing

#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H

//=============================================================================
//
//      var_cache.h
//
//      Variant HAL cache control API
//
//=============================================================================
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// -------------------------------------------
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// Copyright (C) 2006 eCosCentric Ltd.
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// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):     Enrico Piria
// Contributors:
// Date:          2005-25-06
// Purpose:       Definitions specific to the MCF5484 processor cache.
// Usage:         Included via "hal_cache.h". Do not use directly.
//
//####DESCRIPTIONEND####
//========================================================================

#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/coldfire_regs.h>

typedef struct
{
        cyg_uint32      dcache;
        cyg_uint32      icache;
}__attribute__ ((aligned (4), packed))cacr_setting_t;


externC volatile cacr_setting_t cyg_hal_current_cacr_setting; // record current DCACHE and ICACHE setting in CACR
volatile cyg_uint8 cyg_hal_sys_dcache_status; //Record current dcache status, whether it's used or not.
                                                  //1: used; 0: unused.
externC volatile cyg_uint32  cyg_hal_current_acr[4]; // record current car0~car3 setting
// ----------------------------------------------------------------------------
// ACR register bit definition:
// acr register address bit mask definition:
#define MCF548x_CAR_ADMASK_16M        0x00FE0000
#define MCF548x_CAR_ADMASK_32M        0x00FC0000
// enable bit:
#define MCF548x_CAR_E                 0x00008000
// supervisor mode:
#define MCF548x_CAR_S_ALL             (0x03 << 13)
#define MCF548x_CAR_S_USER            0x00000000  // (0x00 << 13)
#define MCF548x_CAR_S_SUPERVISOR      (0x01 << 13)
// address mask mode:
#define MCF548x_CAR_AMM               (0x00000400)
// Cache mode:
#define MCF548x_CAR_CM_WRITETHROUGH   0x00000000 //(0x00 <<5)
#define MCF548x_CAR_CM_COPYBACK       (0x01 << 5)
#define MCF548x_CAR_CM_INHIBITED_PRECISE    (0x02 << 5)
#define MCF548x_CAR_CM_INHIBITED_IMPRECISE  (0x03 << 5)
// supervisor protect:
#define MCF548x_CAR_SP                 0x00000008
// write protect:
#define MCF548x_CAR_W                  0x00000004 //Only CAR0 and CAR1
// ----------------------------------------------------------------------------

// ----------------------------------------------------------------------------
// Cache dimensions - these vary between the ColdFire sub-models

// Data cache
#define HAL_DCACHE_SIZE                 32768   // Size of data cache in bytes  32K-byte data cache

// Size of a data cache line. Leave this value even if there is no data cache
// on 5272, otherwise some tests won't compile.
#define HAL_DCACHE_LINE_SIZE            16

#define HAL_DCACHE_WAYS                 4       // Associativity of the cache

// Instruction cache
#define HAL_ICACHE_SIZE                 32768   // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
#define HAL_ICACHE_WAYS                 4       // Associativity of the cache

#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))

// ----------------------------------------------------------------------------
// Global control of data cache
externC void hal_dcache_enable_reg_setting(void);
externC void hal_dcache_disable_reg_setting(void);
void hal_dcache_flush_all(void);


#define HAL_DCACHE_FLUSH_ALL()       \
        hal_dcache_flush_all()

// Enable the data cache
#define HAL_DCACHE_ENABLE()    \
CYG_MACRO_START                                                                \
   cyg_uint32    _cacr_setval;                                                 \
   HAL_DCACHE_FLUSH_ALL();                                                     \
   HAL_DCACHE_INVALIDATE_ALL();                                                \
   hal_dcache_enable_reg_setting();                                            \
   _cacr_setval = (cyg_uint32)MCF5484_DEVS;                                    \
   _cacr_setval |= 0xc040;                                                     \
   HAL_SET_ACR0(_cacr_setval);                                        \
CYG_MACRO_END

// Disable the data cache
#define HAL_DCACHE_DISABLE()                                         \
CYG_MACRO_START                                                      \
   HAL_DCACHE_FLUSH_ALL();                                            \
   HAL_DCACHE_INVALIDATE_ALL();                                       \
   hal_dcache_disable_reg_setting();                                  \
   HAL_SET_ACR0(0x00);                                                \
CYG_MACRO_END

// Invalidate the entire cache
// Note: Any locked lines will not be invalidated.
#define HAL_DCACHE_INVALIDATE_ALL()   \
CYG_MACRO_START                                                                                             \
   cyg_uint32  _cacr_setval;                                                                                \
   cyg_hal_current_cacr_setting.dcache = ( 0x00 );                                         \
   _cacr_setval = (cyg_hal_current_cacr_setting.dcache | cyg_hal_current_cacr_setting.icache                \
                                               | MCF5484_CACR_DCACHE_DCINVA                                 \
                                               | MCF5484_CACR_DCACHE_BCINVA);                               \
   CYGARC_MOVEC(_cacr_setval, CYGARC_REG_CACR);                                                             \
CYG_MACRO_END

// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC()          \
CYG_MACRO_START                                                                 \
cyg_uint32  _cacr_setval;                                                       \
   _cacr_setval = (cyg_hal_current_cacr_setting.dcache | cyg_hal_current_cacr_setting.icache                \
                                               | MCF5484_CACR_DCACHE_DCINVA                                 \
                                               | MCF5484_CACR_DCACHE_BCINVA);                               \
   CYGARC_MOVEC(_cacr_setval, CYGARC_REG_CACR);                                                             \
CYG_MACRO_END

#define HAL_DCACHE_IS_ENABLED(_state_)                                         \
CYG_MACRO_START                                                                \
        if (cyg_hal_current_cacr_setting.dcache & MCF5484_CACR_DCACHE_DEC)     \
        {                                                                      \
            _state_ = 1;                                                       \
        }else                                                                  \
        {                                                                      \
            _state_ = 0;                                                       \
        }                                                                      \
CYG_MACRO_END

// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)

// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )

//#define HAL_DCACHE_WRITETHRU_MODE       0
//#define HAL_DCACHE_WRITEBACK_MODE       1


// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
#define HAL_DCACHE_LOCK(_base_, _size_)

// Undo a previous lock operation
#define HAL_DCACHE_UNLOCK(_base_, _size_)