📄 mcf5484_devs.h
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#define MCF5484_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30)
#define MCF5484_GPIO_PAR_PSC2_PAR_CTS2_CANRX (0x40)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */
#define MCF5484_GPIO_PAR_PSC1_PAR_TXD1 (0x04)
#define MCF5484_GPIO_PAR_PSC1_PAR_RXD1 (0x08)
#define MCF5484_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4)
#define MCF5484_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6)
#define MCF5484_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00)
#define MCF5484_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80)
#define MCF5484_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0)
#define MCF5484_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00)
#define MCF5484_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
#define MCF5484_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30)
/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */
#define MCF5484_GPIO_PAR_PSC0_PAR_TXD0 (0x04)
#define MCF5484_GPIO_PAR_PSC0_PAR_RXD0 (0x08)
#define MCF5484_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4)
#define MCF5484_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6)
#define MCF5484_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00)
#define MCF5484_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80)
#define MCF5484_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0)
#define MCF5484_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00)
#define MCF5484_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
#define MCF5484_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30)
/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */
#define MCF5484_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0)
#define MCF5484_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2)
#define MCF5484_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS5 (0x1000)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080)
#define MCF5484_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0)
#define MCF5484_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000)
#define MCF5484_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010)
#define MCF5484_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020)
#define MCF5484_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030)
#define MCF5484_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000)
#define MCF5484_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008)
#define MCF5484_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C)
#define MCF5484_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000)
#define MCF5484_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002)
#define MCF5484_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003)
/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
#define MCF5484_GPIO_PAR_TIMER_PAR_TOUT2 (0x01)
#define MCF5484_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1)
#define MCF5484_GPIO_PAR_TIMER_PAR_TOUT3 (0x08)
#define MCF5484_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4)
#define MCF5484_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00)
#define MCF5484_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20)
#define MCF5484_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30)
#define MCF5484_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00)
#define MCF5484_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04)
#define MCF5484_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06)
// ---------------------------------------------------------------------------
//PCI:
// Total size: cyg_uint32 _res[64];
typedef struct
{
// PCI Type 0 Configuration Registers
cyg_uint32 pciidr; // PCI Device ID/Vender ID
cyg_uint32 pciscr; // PCI Status/Command Reg.
cyg_uint32 pciccrir; // PCI Class Code/Revision ID
cyg_uint32 pcicr1; // PCI Configuration 1 Reg.
cyg_uint32 pcibar0; //PCI Base Address Reg0
cyg_uint32 pcibar1; //PCI Base Address Reg1
cyg_uint32 _res1[4];
cyg_uint32 pciccpr; //PCI Cardbus CIS Pointer
cyg_uint32 pcisid; //PCI Subsystem ID/Vender ID
cyg_uint32 pcierbar; //PCI Expansiion ROM
cyg_uint32 pcicpr; //PCI Capabilities Pointer
cyg_uint32 _res2;
cyg_uint32 pcicr2; //PCI Configuration Reg2
cyg_uint32 _res3[8];
//General Control/Status Registers
cyg_uint32 pcigscr; //Global Status/Control Reg.
cyg_uint32 pcitbatr0;//Target Base Address Translation Reg0
cyg_uint32 pcitbatr1;//Target Base Address Translation Reg1
cyg_uint32 pcitcr; //Target Control Reg.
cyg_uint32 pciiw0btar; //Initiator Window 0 Base/Translation Address Register
cyg_uint32 pciiw1btar; //Initiator Window 1 Base/Translation Address Register
cyg_uint32 pciiw2btar; //Initiator Window 2 Base/Translation Address Register
cyg_uint32 _res4;
cyg_uint32 pciiwcr; //Initiator Window Configuration Reg.
cyg_uint32 pciicr; //Initiator Control Reg.
cyg_uint32 pciisr; //Initiator Status Reg.
cyg_uint32 _res5[27];
cyg_uint32 pcicar; //Configuration Address Reg.
cyg_uint32 _res6;
} __attribute__ ((aligned (4), packed)) mcf5484_pci_t;
// ---------------------------------------------------------------------------
//PCI ARB:
typedef struct
{
// Reserved. Presently PCI arbiter not used.
cyg_uint32 _res[64];
} __attribute__ ((aligned (4), packed)) mcf5484_pci_arb_t;
// ---------------------------------------------------------------------------
//EXTDMA External DMA request registers:
typedef struct
{
// Reserved. Presently EXTDMA not used.
cyg_uint32 _res[64];
} __attribute__ ((aligned (4), packed)) mcf5484_extdma_t;
// ---------------------------------------------------------------------------
//Edge port registers:
typedef struct
{
// 0x0F00 EPORT pin assignment register
cyg_uint16 eppar;
// reserved
cyg_uint16 _res1;
//EPORT data direction register, EPORT interrupt enable register
cyg_uint8 epddr;
cyg_uint8 epier;
cyg_uint16 _res2;
//EPORT data register, EPORT pin data register
cyg_uint8 epdr;
cyg_uint8 eppdr;
cyg_uint16 _res3;
//EPORT flag register
cyg_uint8 epfr;
cyg_uint8 _res4[3];
//0x0F10 - 0x0FFF GAP
cyg_uint32 _res5[60];
} __attribute__ ((aligned (4), packed)) mcf5484_eport_t;
//Configuration registers macros
/* Bit definitions and macros for MCF_EPORT_EPPAR */
#define MCF5484_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
#define MCF5484_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
#define MCF5484_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
#define MCF5484_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
#define MCF5484_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
#define MCF5484_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
#define MCF5484_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
#define MCF5484_EPORT_EPPAR_EPPAx_LEVEL (0)
#define MCF5484_EPORT_EPPAR_EPPAx_RISING (1)
#define MCF5484_EPORT_EPPAR_EPPAx_FALLING (2)
#define MCF5484_EPORT_EPPAR_EPPAx_BOTH (3)
/* Bit definitions and macros for MCF_EPORT_EPDDR */
#define MCF5484_EPORT_EPDDR_EPDD1 (0x02)
#define MCF5484_EPORT_EPDDR_EPDD2 (0x04)
#define MCF5484_EPORT_EPDDR_EPDD3 (0x08)
#define MCF5484_EPORT_EPDDR_EPDD4 (0x10)
#define MCF5484_EPORT_EPDDR_EPDD5 (0x20)
#define MCF5484_EPORT_EPDDR_EPDD6 (0x40)
#define MCF5484_EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPIER */
#define MCF5484_EPORT_EPIER_EPIE1 (0x02)
#define MCF5484_EPORT_EPIER_EPIE2 (0x04)
#define MCF5484_EPORT_EPIER_EPIE3 (0x08)
#define MCF5484_EPORT_EPIER_EPIE4 (0x10)
#define MCF5484_EPORT_EPIER_EPIE5 (0x20)
#define MCF5484_EPORT_EPIER_EPIE6 (0x40)
#define MCF5484_EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPDR */
#define MCF5484_EPORT_EPDR_EPD1 (0x02)
#define MCF5484_EPORT_EPDR_EPD2 (0x04)
#define MCF5484_EPORT_EPDR_EPD3 (0x08)
#define MCF5484_EPORT_EPDR_EPD4 (0x10)
#define MCF5484_EPORT_EPDR_EPD5 (0x20)
#define MCF5484_EPORT_EPDR_EPD6 (0x40)
#define MCF5484_EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPPDR */
#define MCF5484_EPORT_EPPDR_EPPD1 (0x02)
#define MCF5484_EPORT_EPPDR_EPPD2 (0x04)
#define MCF5484_EPORT_EPPDR_EPPD3 (0x08)
#define MCF5484_EPORT_EPPDR_EPPD4 (0x10)
#define MCF5484_EPORT_EPPDR_EPPD5 (0x20)
#define MCF5484_EPORT_EPPDR_EPPD6 (0x40)
#define MCF5484_EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPFR */
#define MCF5484_EPORT_EPFR_EPF1 (0x02)
#define MCF5484_EPORT_EPFR_EPF2 (0x04)
#define MCF5484_EPORT_EPFR_EPF3 (0x08)
#define MCF5484_EPORT_EPFR_EPF4 (0x10)
#define MCF5484_EPORT_EPFR_EPF5 (0x20)
#define MCF5484_EPORT_EPFR_EPF6 (0x40)
#define MCF5484_EPORT_EPFR_EPF7 (0x80)
// ---------------------------------------------------------------------------
//Reserve:
typedef struct
{
cyg_uint32 _res1[7104];
} __attribute__ ((aligned (4), packed)) mcf5484_Reserved_7104_t;
// ---------------------------------------------------------------------------
//CTM, Comm Timer register: Used for Baud clock generator
typedef struct
{
cyg_uint32 ctcr[8];
cyg_uint32 _res1[56];
} __attribute__ ((aligned (4), packed)) mcf5484_ctm_t;
// Configuration registers macros
/* Bit definitions and macros for MCF5484_CTM_CTCRFn */
#define MCF5484_CTM_CTCRFn_CRV(x) (((x)&0x0000FFFF)<<0)
#define MCF5484_CTM_CTCRFn_S(x) (((x)&0x0000000F)<<16)
#define MCF5484_CTM_CTCRFn_PCT(x) (((x)&0x00000007)<<20)
#define MCF5484_CTM_CTCRFn_M (0x00800000)
#define MCF5484_CTM_CTCRFn_IM (0x01000000)
#define MCF5484_CTM_CTCRFn_I (0x80000000)
#define MCF5484_CTM_CTCRFn_PCT_100 (0x00000000)
#define MCF5484_CTM_CTCRFn_PCT_50 (0x00100000)
#define MCF5484_CTM_CTCRFn_PCT_25 (0x00200000)
#define MCF5484_CTM_CTCRFn_PCT_12p5 (0x00300000)
#define MCF5484_CTM_CTCRFn_PCT_6p25 (0x00400000)
#define MCF5484_CTM_CTCRFn_PCT_OFF (0x00500000)
#define MCF5484_CTM_CTCRFn_S_CLK_1 (0x00000000)
#define MCF5484_CTM_CTCRFn_S_CLK_2 (0x00010000)
#define MCF5484_CTM_CTCRFn_S_CLK_4 (0x00020000)
#define MCF5484_CTM_CTCRFn_S_CLK_8 (0x00030000)
#define MCF5484_CTM_CTCRFn_S_CLK_16 (0x00040000)
#define MCF5484_CTM_CTCRFn_S_CLK_32 (0x00050000)
#define MCF5484_CTM_CTCRFn_S_CLK_64 (0x00060000)
#define MCF5484_CTM_CTCRFn_S_CLK_128 (0x00070000)
#define MCF5484_CTM_CTCRFn_S_CLK_256 (0x00080000)
/* Bit definitions and macros for MCF5484_CTM_CTCRVn */
#define MCF5484_CTM_CTCRVn_CRV(x) (((x)&0x00FFFFFF)<<0)
#define MCF5484_CTM_CTCRVn_PCT(x) (((x)&0x00000007)<<24)
#define MCF5484_CTM_CTCRVn_M (0x08000000)
#define MCF5484_CTM_CTCRVn_S(x) (((x)&0x0000000F)<<28)
#define MCF5484_CTM_CTCRVn_S_CLK_1 (0x00000000)
#define MCF5484_CTM_CTCRVn_S_CLK_2 (0x10000000)
#define MCF5484_CTM_CTCRVn_S_CLK_4 (0x20000000)
#define MCF5484_CTM_CTCRVn_S_CLK_8 (0x30000000)
#define MCF5484_CTM_CTCRVn_S_CLK_16 (0x40000000)
#define MCF5484_CTM_CTCRVn_S_CLK_32 (0x50000000)
#define MCF5484_CTM_CTCRVn_S_CLK_64 (0x60000000)
#define MCF5484_CTM_CTCRVn_S_CLK_128 (0x70000000)
#define MCF5484_CTM_CTCRVn_S_CLK_256 (0x80000000)
#define MCF5484_CTM_CTCRVn_PCT_100 (0x00000000)
#define MCF5484_CTM_CTCRVn_PCT_50 (0x01000000)
#define MCF5484_CTM_CTCRVn_PCT_25 (0x02000000)
#define MCF5484_CTM_CTCRVn_PCT_12p5 (0x03000000)
#define MCF5484_CTM_CTCRVn_PCT_6p25 (0x04000000)
// ---------------------------------------------------------------------------
//DMA, Multi-channel DMA:
//Toltal size: cyg_uint32 _res1[64];
typedef struct
{
cyg_uint32 TaskBAR; // Task Base Address Register
cyg_uint32 cp; // Current Pointer
cyg_uint32 ep; // End Pointer
cyg_uint32 vp; // Variable Pointer
cyg_uint16 _res1;
cyg_uint16 ptd; // PTD Control Register
cyg_uint32 dipr; // DMA Interrupt Pending Register
cyg_uint32 dimr; // DMA Interrupt Mask Register
cyg_uint16 tcr[16]; // 0 ~ 15 Task Control Regist⌨️ 快捷键说明
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