📄 mcf5484_devs.h
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// Chip-select control register - bank 5
cyg_uint32 cscr5;
//0x0548 - 0x05FF GAP
cyg_uint32 _res1[46];
} __attribute__ ((aligned (4), packed)) mcf5484_fbic_t;
// Configuration registers macros
/* Bit definitions and macros for MCF5484_FBCS_CSAR */
#define MCF5484_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for MCF5484_FBCS_CSMR */
#define MCF5484_FBCS_CSMR_V (0x00000001)
#define MCF5484_FBCS_CSMR_WP (0x00000100)
#define MCF5484_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
#define MCF5484_FBCS_CSMR_BAM_4G (0xFFFF0000)
#define MCF5484_FBCS_CSMR_BAM_2G (0x7FFF0000)
#define MCF5484_FBCS_CSMR_BAM_1G (0x3FFF0000)
#define MCF5484_FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define MCF5484_FBCS_CSMR_BAM_512M (0x1FFF0000)
#define MCF5484_FBCS_CSMR_BAM_256M (0x0FFF0000)
#define MCF5484_FBCS_CSMR_BAM_128M (0x07FF0000)
#define MCF5484_FBCS_CSMR_BAM_64M (0x03FF0000)
#define MCF5484_FBCS_CSMR_BAM_32M (0x01FF0000)
#define MCF5484_FBCS_CSMR_BAM_16M (0x00FF0000)
#define MCF5484_FBCS_CSMR_BAM_8M (0x007F0000)
#define MCF5484_FBCS_CSMR_BAM_4M (0x003F0000)
#define MCF5484_FBCS_CSMR_BAM_2M (0x001F0000)
#define MCF5484_FBCS_CSMR_BAM_1M (0x000F0000)
#define MCF5484_FBCS_CSMR_BAM_1024K (0x000F0000)
#define MCF5484_FBCS_CSMR_BAM_512K (0x00070000)
#define MCF5484_FBCS_CSMR_BAM_256K (0x00030000)
#define MCF5484_FBCS_CSMR_BAM_128K (0x00010000)
#define MCF5484_FBCS_CSMR_BAM_64K (0x00000000)
/* Bit definitions and macros for MCF5484_FBCS_CSCR */
#define MCF5484_FBCS_CSCR_BSTW (0x00000008)
#define MCF5484_FBCS_CSCR_BSTR (0x00000010)
#define MCF5484_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
#define MCF5484_FBCS_CSCR_AA (0x00000100)
#define MCF5484_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
#define MCF5484_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
#define MCF5484_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
#define MCF5484_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
#define MCF5484_FBCS_CSCR_SWSEN (0x00800000)
#define MCF5484_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
#define MCF5484_FBCS_CSCR_PS_8 (0x0040)
#define MCF5484_FBCS_CSCR_PS_16 (0x0080)
#define MCF5484_FBCS_CSCR_PS_32 (0x0000)
// ---------------------------------------------------------------------------
//Reserved:
typedef struct
{
// Reserved.
cyg_uint32 _res[64];
} __attribute__ ((aligned (4), packed)) mcf5484_Reserved_64_t;
// ---------------------------------------------------------------------------
// Interrupt controller registers:
typedef struct
{
//0x700 Interrupt pending register High[63:32]
cyg_uint32 iprh;
//0x704 Interrupt pending register LOW[31:0]
cyg_uint32 iprl;
//0x708 Interrupt Mask register High[63:32]
cyg_uint32 imrh;
//0x70c Interrupt Mask register High[31:0]
cyg_uint32 imrl;
// Interrupt Force register High[63:32]
cyg_uint32 intfrch;
// Interrupt Force register Low[31:0]
cyg_uint32 intfrcl;
// interrupt request level register
cyg_uint8 irlr;
// interrupt acknowledge level and priority register
cyg_uint8 acklpr;
// reserved
cyg_uint16 _res1;
// 0x71C - 0x73F reserved
cyg_uint32 _res2[9];
// reserved
cyg_uint8 _res_icr;
// interrupt control register 1~63, icr[0] is Interrupt 65
// There are 63 usable interrupt sources that are corrsponding with ICR.
cyg_uint8 icr[63];
// reserved
cyg_uint32 _res3[24];
// Software IACK register
cyg_uint8 swiack;
// reserved
cyg_uint8 _res4[3];
// Level 1 IACK register
cyg_uint8 l1iack;
// reserved
cyg_uint8 _res5[3];
// Level 2 IACK register
cyg_uint8 l2iack;
// reserved
cyg_uint8 _res6[3];
// Level 3 IACK register
cyg_uint8 l3iack;
// reserved
cyg_uint8 _res7[3];
// Level 4 IACK register
cyg_uint8 l4iack;
// reserved
cyg_uint8 _res8[3];
// Level 5 IACK register
cyg_uint8 l5iack;
// reserved
cyg_uint8 _res9 [3];
// Level 6 IACK register
cyg_uint8 l6iack;
// reserved
cyg_uint8 _res10 [3];
// Level 7 IACK register
cyg_uint8 l7iack;
// reserved
cyg_uint8 _res11 [3];
} __attribute__ ((aligned (4), packed)) mcf5484_intc_t;
//Configuration registers macros
#define MCF5484_INTC_IMRL_MASKALL(x) (((x)&0x01)<<0)
#define MCF5484_INTC_IRLR_IRQ 0xFE
#define MCF5484_INTC_IACKLPR_LEVEL 0x70
#define MCF5484_INTC_IACKLPR_PRI 0x0F
#define MCF5484_INTC_ICR_IL(x) (((x)&0x07)<<3)
#define MCF5484_INTC_ICR_IP(x) (((x)&0x07)<<0)
// ---------------------------------------------------------------------------
// GPT module:
// Total size: cyg_uint32 _res[64];
typedef struct
{
cyg_uint32 gms0; // GPT Enable and Mode Select Register
cyg_uint32 gcir0; // GPT Counter input register
cyg_uint32 gpwm0; // GPT PWM Configuration regisre
cyg_uint32 gsr0; // GPT status register
cyg_uint32 gms1; // GPT Enable and Mode Select Register
cyg_uint32 gcir1; // GPT Counter input register
cyg_uint32 gpwm1; // GPT PWM Configuration regisre
cyg_uint32 gsr1; // GPT status register
cyg_uint32 gms2; // GPT Enable and Mode Select Register
cyg_uint32 gcir2; // GPT Counter input register
cyg_uint32 gpwm2; // GPT PWM Configuration regisre
cyg_uint32 gsr2; // GPT status register
cyg_uint32 gms3; // GPT Enable and Mode Select Register
cyg_uint32 gcir3; // GPT Counter input register
cyg_uint32 gpwm3; // GPT PWM Configuration regisre
cyg_uint32 gsr3; // GPT status register
cyg_uint32 _res[48];
} __attribute__ ((aligned (4), packed)) mcf5484_gpt_t;
#define MCF5484_GPT_GMS_OCPW_RESET 0xA5000000
#define MCF5484_GPT_GMS_WDEN 0x08000 // Watchdog enable
#define MCF5484_GPT_GMS_CE 0x01000 // Counter enable
#define MCF5484_GPT_GMS_IEN 0x0100 // Interrupt enable
#define MCF5484_GPT_GMS_TMS_INTERANL_TIMER 0x04 // Internal timer mode
#define MCF5484_GPT_GSR_TEXP_MSK 0x08
// ---------------------------------------------------------------------------
// Slice Timer module:
typedef struct
{
// 0x0900 SLT Terminal Count Register
cyg_uint32 stcnt;
// SLT Control Register
cyg_uint32 scr;
// SLT Count Value Register
cyg_uint32 scnt;
// SLT Status Register
cyg_uint32 ssr;
} __attribute__ ((aligned (4), packed)) mcf5484_slt_t;
//Configuration registers macros
/* Bit definitions and macros for MCF_SLT_SCR */
#define MCF5484_SLT_SCR_TEN (0x01000000)
#define MCF5484_SLT_SCR_IEN (0x02000000)
#define MCF5484_SLT_SCR_RUN (0x04000000)
/* Bit definitions and macros for MCF_SLT_SSR */
#define MCF5484_SLT_SSR_ST (0x01000000)
#define MCF5484_SLT_SSR_BE (0x02000000)
// ---------------------------------------------------------------------------
//GPIO:
typedef struct
{
// 0x0A00 - 0x0A0C Port Output Data Register
cyg_uint8 podr_fbctl;
cyg_uint8 podr_fbcs;
cyg_uint8 podr_dma;
cyg_uint8 _res1;
cyg_uint8 podr_fec0h;
cyg_uint8 podr_fec0l;
cyg_uint8 podr_fec1h;
cyg_uint8 podr_fec1l;
cyg_uint8 podr_feci2c;
cyg_uint8 podr_pcibg;
cyg_uint8 podr_pcibr;
cyg_uint8 _res2;
cyg_uint8 podr_psc3psc2;
cyg_uint8 podr_psc1psc0;
cyg_uint8 podr_dspi;
cyg_uint8 _res3;
// Port Data Direction Registers
cyg_uint8 pddr_fbctl;
cyg_uint8 pddr_fbcs;
cyg_uint8 pddr_dma;
cyg_uint8 _res4;
cyg_uint8 pddr_fec0h;
cyg_uint8 pddr_fec0l;
cyg_uint8 pddr_fec1h;
cyg_uint8 pddr_fec1l;
cyg_uint8 pddr_feci2c;
cyg_uint8 pddr_pcibg;
cyg_uint8 pddr_pcibr;
cyg_uint8 _res5;
cyg_uint8 pddr_psc3psc2;
cyg_uint8 pddr_psc1psc0;
cyg_uint8 pddr_dspi;
cyg_uint8 _res6;
// Port pin Data/Set Data register
cyg_uint8 ppdsdr_fbctl;
cyg_uint8 ppdsdr_fbcs;
cyg_uint8 ppdsdr_dma;
cyg_uint8 _res7;
cyg_uint8 ppdsdr_fec0h;
cyg_uint8 ppdsdr_fec0l;
cyg_uint8 ppdsdr_fec1h;
cyg_uint8 ppdsdr_fec1l;
cyg_uint8 ppdsdr_feci2c;
cyg_uint8 ppdsdr_pcibg;
cyg_uint8 ppdsdr_pcibr;
cyg_uint8 _res8;
cyg_uint8 ppdsdr_psc3psc2;
cyg_uint8 ppdsdr_psc1psc0;
cyg_uint8 ppdsdr_dspi;
cyg_uint8 _res9;
// Port Clear Output Data Register
cyg_uint8 pclrr_fbctl;
cyg_uint8 pclrr_fbcs;
cyg_uint8 pclrr_dma;
cyg_uint8 _res10;
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