mcf5484_devs.h

实现快速傅立叶变换算法,provides test framwork for FFT testing

#ifndef CYGONCE_MCF5484_DEVS_H
#define CYGONCE_MCF5484_DEVS_H

//=============================================================================
//
//      mcf5484_devs.h
//
//      Definitions for the MCF5484 on-chip peripherals
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2006 eCosCentric Ltd.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):     Enrico Piria, Wade Jensen, WangLei
// Contributors:
// Date:          2005-25-06
// Purpose:       Definitions for the MCF5484 on-chip peripherals.
// Usage:         #include <cyg/hal/mcf5484_devs.h>
//
//####DESCRIPTIONEND####
//========================================================================

#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>

// General configuration registers
typedef struct
{
    // Module base  address  register
    cyg_uint32 	mbar;

    // SDRAM Drive Strength Register
    cyg_uint32	sdramds;

    // reserved
    cyg_uint32	_res1[2];
    
    // system breakpoint control register
    cyg_uint32	sbcr;

    // reserved
    cyg_uint32 	_res2[3];

    // SDRAM Chip Select 0~3 configuration register
    cyg_uint32	cscfg[4];
      
    // reserved
    cyg_uint32 	_res4[2];
    
    //Sequential Access Control register
    cyg_uint32 	secsacr;
    
    // reserved
    cyg_uint32 	_res5[2];
    	
    //Reset Status Register
    cyg_uint32 	rsr;
    
    //reserved
    cyg_uint32	_res6[2];
    
    //JTAG Device Identification Number
    cyg_uint32	jtagid;

    //0x54 -0xFF GAP 
    cyg_uint32	_res7[43];
} __attribute__ ((aligned (4), packed)) mcf5484_siu_t;

// Configuration registers macros


#define MCF5484_SIU_SBCR_PIN2CPU(x)            (((x)&0x01)<<31)
#define MCF5484_SIU_SBCR_PIN2DMA(x)            (((x)&0x01)<<30)
#define MCF5484_SIU_SBCR_CPU2DMA(x)            (((x)&0x01)<<29)
#define MCF5484_SIU_SBCR_DMA2CPU(x)            (((x)&0x01)<<28)
#define MCF5484_SIU_SBCR_PIN2DSPI(x)           (((x)&0x01)<<27)


#define MCF5484_SIU_SECSACR_SEQEN   0x0001

#define MCF5484_SIU_RSR_RSTJTG(x)              (((x)&0x01)<<3)
#define MCF5484_SIU_RSR_RSTWD(x)               (((x)&0x01)<<1)                   //General purpose watchdog timer reset asserted.
#define MCF5484_SIU_RSR_RST(x)                 (((x)&0x01)<<0)

// ---------------------------------------------------------------------------
// SDRAM control register
typedef struct
{
    // 0x0100 Mode/Externded Mode Register
    cyg_uint32 	sdmr;

    // SDRAM Control Register
   cyg_uint32 	sdcr;

    // SDRAM configuration register
    cyg_uint32	sdcfg1;
   
    // SDRAM configuration register
    cyg_uint32	sdcfg2;
    
    // 0x0110 -0x 01FF GAP
    cyg_uint32	_res1[60];
} __attribute__ ((aligned (4), packed)) mcf5484_sdramc_t;

// Configuration registers macros
/* Bit definitions and macros for MCF5484_SDRAMC_SDRAMDS */
#define MCF5484_SDRAMC_SDRAMDS_SB_D(x)         (((x)&0x00000003)<<0)
#define MCF5484_SDRAMC_SDRAMDS_SB_S(x)         (((x)&0x00000003)<<2)
#define MCF5484_SDRAMC_SDRAMDS_SB_A(x)         (((x)&0x00000003)<<4)
#define MCF5484_SDRAMC_SDRAMDS_SB_C(x)         (((x)&0x00000003)<<6)
#define MCF5484_SDRAMC_SDRAMDS_SB_E(x)         (((x)&0x00000003)<<8)
//#define MCF5484_SDRAMC_SDRAMDS_DRIVE_8MA       (0x10)
//#define MCF5484_SDRAMC_SDRAMDS_DRIVE_16MA      (0x01)
//#define MCF5484_SDRAMC_SDRAMDS_DRIVE_24MA      (0x00)
//#define MCF5484_SDRAMC_SDRAMDS_DRIVE_NONE      (0x03)
#define MCF5484_SDRAMC_SDRAMDS_DRIVE_8MA       (0x2)
#define MCF5484_SDRAMC_SDRAMDS_DRIVE_16MA      (0x1)
#define MCF5484_SDRAMC_SDRAMDS_DRIVE_24MA      (0x0)
#define MCF5484_SDRAMC_SDRAMDS_DRIVE_NONE      (0x3)

/* Bit definitions and macros for MCF5484_SDRAMC_CSnCFG */
#define MCF5484_SDRAMC_CSnCFG_CSSZ(x)          (((x)&0x0000001F)<<0)
#define MCF5484_SDRAMC_CSnCFG_CSBA(x)          (((x)&0x00000FFF)<<20)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_DIABLE      (0x00000000)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_1MBYTE      (0x00000013)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_2MBYTE      (0x00000014)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_4MBYTE      (0x00000015)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_8MBYTE      (0x00000016)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_16MBYTE     (0x00000017)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_32MBYTE     (0x00000018)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_64MBYTE     (0x00000019)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_128MBYTE    (0x0000001A)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_256MBYTE    (0x0000001B)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_512MBYTE    (0x0000001C)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_1GBYTE      (0x0000001D)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_2GBYTE      (0x0000001E)
#define MCF5484_SDRAMC_CSnCFG_CSSZ_4GBYTE      (0x0000001F)

/* Bit definitions and macros for MCF5484_SDRAMC_SDMR */
#define MCF5484_SDRAMC_SDMR_CMD                (0x00010000)
//#define MCF5484_SDRAMC_SDMR_AD(x)              (((x)&0x00000FFF)<<18)
#define MCF5484_SDRAMC_SDMR_AD(x)              (((x)&0x00000FFF)<<16)	//mapoma
#define MCF5484_SDRAMC_SDMR_BNKAD(x)           (((x)&0x00000003)<<30)
#define MCF5484_SDRAMC_SDMR_BNKAD_LMR          (0x00000000)
#define MCF5484_SDRAMC_SDMR_BNKAD_LEMR         (0x40000000)

/* Bit definitions and macros for MCF5484_SDRAMC_SDCR */
#define MCF5484_SDRAMC_SDCR_IPALL              (0x00000002)
#define MCF5484_SDRAMC_SDCR_IREF               (0x00000004)
#define MCF5484_SDRAMC_SDCR_BUFF               (0x00000010)
#define MCF5484_SDRAMC_SDCR_DQS_OE(x)          (((x)&0x0000000F)<<8)
#define MCF5484_SDRAMC_SDCR_RCNT(x)            (((x)&0x0000003F)<<16)
#define MCF5484_SDRAMC_SDCR_DRIVE              (0x00400000)
#define MCF5484_SDRAMC_SDCR_AP                 (0x00800000)
#define MCF5484_SDRAMC_SDCR_MUX(x)             (((x)&0x00000003)<<24)
#define MCF5484_SDRAMC_SDCR_REF                (0x10000000)
#define MCF5484_SDRAMC_SDCR_DDR                (0x20000000)
#define MCF5484_SDRAMC_SDCR_CKE                (0x40000000)
#define MCF5484_SDRAMC_SDCR_MODE_EN            (0x80000000)

/* Bit definitions and macros for MCF5484_SDRAMC_SDCFG1 */
#define MCF5484_SDRAMC_SDCFG1_WTLAT(x)         (((x)&0x00000007)<<4)
#define MCF5484_SDRAMC_SDCFG1_REF2ACT(x)       (((x)&0x0000000F)<<8)
#define MCF5484_SDRAMC_SDCFG1_PRE2ACT(x)       (((x)&0x00000007)<<12)
#define MCF5484_SDRAMC_SDCFG1_ACT2RW(x)        (((x)&0x00000007)<<16)
#define MCF5484_SDRAMC_SDCFG1_RDLAT(x)         (((x)&0x0000000F)<<20)
#define MCF5484_SDRAMC_SDCFG1_SWT2RD(x)        (((x)&0x00000007)<<24)
#define MCF5484_SDRAMC_SDCFG1_SRD2RW(x)        (((x)&0x0000000F)<<28)

/* Bit definitions and macros for MCF5484_SDRAMC_SDCFG2 */
#define MCF5484_SDRAMC_SDCFG2_BL(x)            (((x)&0x0000000F)<<16)
#define MCF5484_SDRAMC_SDCFG2_BRD2WT(x)        (((x)&0x0000000F)<<20)
#define MCF5484_SDRAMC_SDCFG2_BWT2RW(x)        (((x)&0x0000000F)<<24)
#define MCF5484_SDRAMC_SDCFG2_BRD2PRE(x)       (((x)&0x0000000F)<<28)

// ---------------------------------------------------------------------------
//XARB:
//Toltal size: cyg_uint32 _res[64];
typedef struct
{
    cyg_uint32    _res1[16];
    cyg_uint32    xarb_cfg;
    cyg_uint32    xarb_ver;
    cyg_uint32    xarb_sr;
    cyg_uint32    xarb_imr;
    cyg_uint32    xarb_adrcap; // Arbiter Address Capture
    cyg_uint32    xarb_sigcap; // Arbiter Signal Capture
    cyg_uint32    xarb_adrto;  // Arbiter address Timout
    cyg_uint32    xarb_datto;  // Arbiter Data Timeout
    cyg_uint32    xarb_busto;  // Arbiter Bus Timout
    cyg_uint32    xarb_prien;  // Arbiter Master Priority Enable
    cyg_uint32    xarb_pri;    // Arbiter Master Priority
    cyg_uint32    _res2[37];

} __attribute__ ((aligned (4), packed)) mcf5484_xarb_t;

// ---------------------------------------------------------------------------
//Reserved:
typedef struct
{

    // Reserved.
    cyg_uint32 _res[128];

} __attribute__ ((aligned (4), packed)) mcf5484_Reserved_128_t;

//-------------------------------------------------------------------------------
//FlexBus:
typedef struct
{
    // 0x0500 Chip-select address register - bank 0
    cyg_uint32 	csar0;

    // Chip-select mask register - bank 0
   cyg_uint32 	csmr0;

    // Chip-select control register - bank 0
    cyg_uint32	cscr0;
   
   // Chip-select address register - bank 1
    cyg_uint32 	csar1;

    // Chip-select mask register - bank 1
    cyg_uint32 	csmr1;

    // Chip-select control register - bank 1
    cyg_uint32	cscr1;

    // Chip-select address register - bank 2
    cyg_uint32 	csar2;

    // Chip-select mask register - bank 2
    cyg_uint32 	csmr2;

    // Chip-select control register - bank 2
    cyg_uint32	cscr2;

    // Chip-select address register - bank 3
    cyg_uint32 	csar3;

    // Chip-select mask register - bank 3
    cyg_uint32 	csmr3;

    // Chip-select control register - bank 3
    cyg_uint32	cscr3;

    // Chip-select address register - bank 4
    cyg_uint32 	csar4;

    // Chip-select mask register - bank 4
    cyg_uint32 	csmr4;
    
    // Chip-select control register - bank 4
    cyg_uint32	cscr4;
    
    // Chip-select address register - bank 5
    cyg_uint32 	csar5;
    
    // Chip-select mask register - bank 5
    cyg_uint32 	csmr5;