📄 mc68hc908jb16.h
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/* Based on CPU DB MC68HC908JB16, version 2.89.005 (RegistersPrg V1.061) */
#ifndef _MC68HC908JB16_H
#define _MC68HC908JB16_H
/* Types definition */
typedef unsigned char byte;
typedef unsigned int word;
typedef unsigned long dword;
typedef unsigned long dlong[2];
#ifndef __RESET_WATCHDOG_MACRO
#define __RESET_WATCHDOG_MACRO
/* Watchdog reset macro */
#ifdef _lint
#define __RESET_WATCHDOG() /* empty */
#else
#define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */
#endif
#endif /* __RESET_WATCHDOG_MACRO */
#define REG_BASE 0x0000 /* Base address for the I/O register block */
#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */
/**************** interrupt vector table ****************/
#define INT_KBI 0x0000FFE0
#define INT_SCITransmit 0x0000FFE2
#define INT_SCIReceive 0x0000FFE4
#define INT_SCIError 0x0000FFE6
#define INT_TIM2Ovr 0x0000FFE8
#define INT_TIM2CH01 0x0000FFEA
#define INT_TIM2CH1 0x0000FFEC
#define INT_TIM2CH0 0x0000FFEE
#define INT_TIM1Ovr 0x0000FFF0
#define INT_TIM1CH01 0x0000FFF2
#define INT_TIM1CH1 0x0000FFF4
#define INT_TIM1CH0 0x0000FFF6
#define INT_IRQ 0x0000FFF8
#define INT_USB 0x0000FFFA
#define INT_SWI 0x0000FFFC
#define INT_RESET 0x0000FFFE
/**************** registers I/O map ****************/
/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
byte Byte;
struct {
byte PTA0 :1; /* Port A Data Bit 0 */
byte PTA1 :1; /* Port A Data Bit 1 */
byte PTA2 :1; /* Port A Data Bit 2 */
byte PTA3 :1; /* Port A Data Bit 3 */
byte PTA4 :1; /* Port A Data Bit 4 */
byte PTA5 :1; /* Port A Data Bit 5 */
byte PTA6 :1; /* Port A Data Bit 6 */
byte PTA7 :1; /* Port A Data Bit 7 */
} Bits;
struct {
byte grpPTA :8;
} MergedBits;
} PTASTR;
extern volatile PTASTR _PTA @0x00000000;
#define PTA _PTA.Byte
#define PTA_PTA0 _PTA.Bits.PTA0
#define PTA_PTA1 _PTA.Bits.PTA1
#define PTA_PTA2 _PTA.Bits.PTA2
#define PTA_PTA3 _PTA.Bits.PTA3
#define PTA_PTA4 _PTA.Bits.PTA4
#define PTA_PTA5 _PTA.Bits.PTA5
#define PTA_PTA6 _PTA.Bits.PTA6
#define PTA_PTA7 _PTA.Bits.PTA7
#define PTA_PTA _PTA.MergedBits.grpPTA
#define PTA_PTA0_MASK 1
#define PTA_PTA0_BITNUM 0
#define PTA_PTA1_MASK 2
#define PTA_PTA1_BITNUM 1
#define PTA_PTA2_MASK 4
#define PTA_PTA2_BITNUM 2
#define PTA_PTA3_MASK 8
#define PTA_PTA3_BITNUM 3
#define PTA_PTA4_MASK 16
#define PTA_PTA4_BITNUM 4
#define PTA_PTA5_MASK 32
#define PTA_PTA5_BITNUM 5
#define PTA_PTA6_MASK 64
#define PTA_PTA6_BITNUM 6
#define PTA_PTA7_MASK 128
#define PTA_PTA7_BITNUM 7
#define PTA_PTA_MASK 255
#define PTA_PTA_BITNUM 0
/*** PTC - Port C Data Register; 0x00000002 ***/
typedef union {
byte Byte;
struct {
byte PTC0 :1; /* Port C Data Bit 0 */
byte PTC1 :1; /* Port C Data Bit 1 */
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
struct {
byte grpPTC :2;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} PTCSTR;
extern volatile PTCSTR _PTC @0x00000002;
#define PTC _PTC.Byte
#define PTC_PTC0 _PTC.Bits.PTC0
#define PTC_PTC1 _PTC.Bits.PTC1
#define PTC_PTC _PTC.MergedBits.grpPTC
#define PTC_PTC0_MASK 1
#define PTC_PTC0_BITNUM 0
#define PTC_PTC1_MASK 2
#define PTC_PTC1_BITNUM 1
#define PTC_PTC_MASK 3
#define PTC_PTC_BITNUM 0
/*** PTD - Port D Data Register; 0x00000003 ***/
typedef union {
byte Byte;
struct {
byte PTD0 :1; /* Port D Data Bit 0 */
byte PTD1 :1; /* Port D Data Bit 1 */
byte PTD2 :1; /* Port D Data Bit 2 */
byte PTD3 :1; /* Port D Data Bit 3 */
byte PTD4 :1; /* Port D Data Bit 4 */
byte PTD5 :1; /* Port D Data Bit 5 */
byte :1;
byte :1;
} Bits;
struct {
byte grpPTD :6;
byte :1;
byte :1;
} MergedBits;
} PTDSTR;
extern volatile PTDSTR _PTD @0x00000003;
#define PTD _PTD.Byte
#define PTD_PTD0 _PTD.Bits.PTD0
#define PTD_PTD1 _PTD.Bits.PTD1
#define PTD_PTD2 _PTD.Bits.PTD2
#define PTD_PTD3 _PTD.Bits.PTD3
#define PTD_PTD4 _PTD.Bits.PTD4
#define PTD_PTD5 _PTD.Bits.PTD5
#define PTD_PTD _PTD.MergedBits.grpPTD
#define PTD_PTD0_MASK 1
#define PTD_PTD0_BITNUM 0
#define PTD_PTD1_MASK 2
#define PTD_PTD1_BITNUM 1
#define PTD_PTD2_MASK 4
#define PTD_PTD2_BITNUM 2
#define PTD_PTD3_MASK 8
#define PTD_PTD3_BITNUM 3
#define PTD_PTD4_MASK 16
#define PTD_PTD4_BITNUM 4
#define PTD_PTD5_MASK 32
#define PTD_PTD5_BITNUM 5
#define PTD_PTD_MASK 63
#define PTD_PTD_BITNUM 0
/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
byte Byte;
struct {
byte DDRA0 :1; /* Data Direction Register A Bit 0 */
byte DDRA1 :1; /* Data Direction Register A Bit 1 */
byte DDRA2 :1; /* Data Direction Register A Bit 2 */
byte DDRA3 :1; /* Data Direction Register A Bit 3 */
byte DDRA4 :1; /* Data Direction Register A Bit 4 */
byte DDRA5 :1; /* Data Direction Register A Bit 5 */
byte DDRA6 :1; /* Data Direction Register A Bit 6 */
byte DDRA7 :1; /* Data Direction Register A Bit 7 */
} Bits;
struct {
byte grpDDRA :8;
} MergedBits;
} DDRASTR;
extern volatile DDRASTR _DDRA @0x00000004;
#define DDRA _DDRA.Byte
#define DDRA_DDRA0 _DDRA.Bits.DDRA0
#define DDRA_DDRA1 _DDRA.Bits.DDRA1
#define DDRA_DDRA2 _DDRA.Bits.DDRA2
#define DDRA_DDRA3 _DDRA.Bits.DDRA3
#define DDRA_DDRA4 _DDRA.Bits.DDRA4
#define DDRA_DDRA5 _DDRA.Bits.DDRA5
#define DDRA_DDRA6 _DDRA.Bits.DDRA6
#define DDRA_DDRA7 _DDRA.Bits.DDRA7
#define DDRA_DDRA _DDRA.MergedBits.grpDDRA
#define DDRA_DDRA0_MASK 1
#define DDRA_DDRA0_BITNUM 0
#define DDRA_DDRA1_MASK 2
#define DDRA_DDRA1_BITNUM 1
#define DDRA_DDRA2_MASK 4
#define DDRA_DDRA2_BITNUM 2
#define DDRA_DDRA3_MASK 8
#define DDRA_DDRA3_BITNUM 3
#define DDRA_DDRA4_MASK 16
#define DDRA_DDRA4_BITNUM 4
#define DDRA_DDRA5_MASK 32
#define DDRA_DDRA5_BITNUM 5
#define DDRA_DDRA6_MASK 64
#define DDRA_DDRA6_BITNUM 6
#define DDRA_DDRA7_MASK 128
#define DDRA_DDRA7_BITNUM 7
#define DDRA_DDRA_MASK 255
#define DDRA_DDRA_BITNUM 0
/*** DDRC - Data Direction Register C; 0x00000006 ***/
typedef union {
byte Byte;
struct {
byte DDRC0 :1; /* Data Direction Register C Bit 0 */
byte DDRC1 :1; /* Data Direction Register C Bit 1 */
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
struct {
byte grpDDRC :2;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} DDRCSTR;
extern volatile DDRCSTR _DDRC @0x00000006;
#define DDRC _DDRC.Byte
#define DDRC_DDRC0 _DDRC.Bits.DDRC0
#define DDRC_DDRC1 _DDRC.Bits.DDRC1
#define DDRC_DDRC _DDRC.MergedBits.grpDDRC
#define DDRC_DDRC0_MASK 1
#define DDRC_DDRC0_BITNUM 0
#define DDRC_DDRC1_MASK 2
#define DDRC_DDRC1_BITNUM 1
#define DDRC_DDRC_MASK 3
#define DDRC_DDRC_BITNUM 0
/*** DDRD - Data Direction Register D; 0x00000007 ***/
typedef union {
byte Byte;
struct {
byte DDRD0 :1; /* Data Direction Register D Bit 0 */
byte DDRD1 :1; /* Data Direction Register D Bit 1 */
byte DDRD2 :1; /* Data Direction Register D Bit 2 */
byte DDRD3 :1; /* Data Direction Register D Bit 3 */
byte DDRD4 :1; /* Data Direction Register D Bit 4 */
byte DDRD5 :1; /* Data Direction Register D Bit 5 */
byte :1;
byte :1;
} Bits;
struct {
byte grpDDRD :6;
byte :1;
byte :1;
} MergedBits;
} DDRDSTR;
extern volatile DDRDSTR _DDRD @0x00000007;
#define DDRD _DDRD.Byte
#define DDRD_DDRD0 _DDRD.Bits.DDRD0
#define DDRD_DDRD1 _DDRD.Bits.DDRD1
#define DDRD_DDRD2 _DDRD.Bits.DDRD2
#define DDRD_DDRD3 _DDRD.Bits.DDRD3
#define DDRD_DDRD4 _DDRD.Bits.DDRD4
#define DDRD_DDRD5 _DDRD.Bits.DDRD5
#define DDRD_DDRD _DDRD.MergedBits.grpDDRD
#define DDRD_DDRD0_MASK 1
#define DDRD_DDRD0_BITNUM 0
#define DDRD_DDRD1_MASK 2
#define DDRD_DDRD1_BITNUM 1
#define DDRD_DDRD2_MASK 4
#define DDRD_DDRD2_BITNUM 2
#define DDRD_DDRD3_MASK 8
#define DDRD_DDRD3_BITNUM 3
#define DDRD_DDRD4_MASK 16
#define DDRD_DDRD4_BITNUM 4
#define DDRD_DDRD5_MASK 32
#define DDRD_DDRD5_BITNUM 5
#define DDRD_DDRD_MASK 63
#define DDRD_DDRD_BITNUM 0
/*** PTE - Port E Data Register; 0x00000008 ***/
typedef union {
byte Byte;
struct {
byte PTE0 :1; /* Port E Data Bit 0 */
byte PTE1 :1; /* Port E Data Bit 1 */
byte PTE2 :1; /* Port E Data Bit 2 */
byte PTE3 :1; /* Port E Data Bit 3 */
byte PTE4 :1; /* Port E Data Bit 4 */
byte :1;
byte :1;
byte :1;
} Bits;
struct {
byte grpPTE :5;
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