class.ptf

DE2板子附带的VGA IPCORE 有兴趣的朋友可以下载

               align = "left";
               title = "<b>Binary_VGA_Controller 1.0</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2006.07.19.01:51:27";
               }
               TEXT 
               {
                  title = "Class name: binary_vga_controller";
               }
               TEXT 
               {
                  title = "Class version: 1.0";
               }
               TEXT 
               {
                  title = "Component name: Binary_VGA_Controller";
               }
               TEXT 
               {
                  title = "Component Group: Terasic Technologies Inc";
               }
               GROUP parameters
               {
                  title = "Parameters";
                  layout = "form";
                  align = "left";
                  EDIT e1
                  {
                     id = "RAM_SIZE";
                     editable = "1";
                     title = "RAM_SIZE:";
                     columns = "40";
                     tooltip = "default value: 19'b1001011000000000000";
                     DATA 
                     {
                        $H/ram_size = "$";
                     }
                     q = "'";
                     warning = "{{ if(!(regexp('ugly_'+$H/ram_size,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/ram_size,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/ram_size,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/ram_size,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/ram_size,'ugly_-?[0-9]+')))'RAM_SIZE must be numeric constant, not '+$H/ram_size; }}";
                  }
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "6.00";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
         HDL_PARAMETER ram_size
         {
            parameter_name = "RAM_SIZE";
            type = "integer";
            default_value = "19'b1001011000000000000";
            editable = "1";
            tooltip = "";
         }
      }
      SW_FILES 
      {
         FILE 
         {
            filepath = "inc/VGA.c";
            type = "Registers (inc/)";
         }
         FILE 
         {
            filepath = "inc/VGA.h";
            type = "Registers (inc/)";
         }
      }
      built_on = "2006.07.19.01:51:27";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE Img_RAM.v
         {
            file_mod = "Mon Sep 12 06:56:20 CST 2005";
            quartus_map_start = "Tue Jul 18 04:16:56 CST 2006";
            quartus_map_finished = "Tue Jul 18 04:16:59 CST 2006";
            #found 1 valid modules
            WRAPPER Img_RAM
            {
               CLASS Img_RAM
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "C:/DE2/DE2_NIOS_NET/user_logic_VGA_Controller/Img_RAM.v";
                        }
                     }
                     top_module_name = "Img_RAM";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "Img_RAM";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT data
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT wren
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT wraddress
                           {
                              width = "19";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT rdaddress
                           {
                              width = "16";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT wrclock
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT rdclock
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT q
                           {
                              width = "8";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "Img_RAM";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
               }
            }
         }
         FILE VGA_Controller.v
         {
            file_mod = "Tue Jul 18 04:13:22 CST 2006";
            quartus_map_start = "Tue Jul 18 04:17:00 CST 2006";
            quartus_map_finished = "Tue Jul 18 04:17:03 CST 2006";
            #found 0 valid modules
         }
         FILE VGA_NIOS_CTRL.v
         {
            file_mod = "Tue Jul 18 04:16:26 CST 2006";
            quartus_map_start = "Tue Jul 18 04:17:03 CST 2006";
            quartus_map_finished = "Tue Jul 18 04:17:06 CST 2006";
            #found 1 valid modules
            WRAPPER VGA_NIOS_CTRL
            {
               CLASS VGA_NIOS_CTRL
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "C:/DE2/DE2_NIOS_NET/user_logic_VGA_Controller/VGA_NIOS_CTRL.v";
                        }
                     }
                     top_module_name = "VGA_NIOS_CTRL";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "VGA_NIOS_CTRL";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT oDATA
                           {
                              width = "16";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iDATA
                           {
                              width = "16";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iADDR
                           {
                              width = "19";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iWR
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iRD
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iCS
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iCLK
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iRST_N
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT VGA_R
                           {
                              width = "10";
                              width_expression = "";
                              direction = "output";
                              type = "export";