f280xbldcpwm.c

DSP280X芯片的编程简单例子

/* ==================================================================================
File name:       F280XBLDCPWM.C
                    
Originator:	Digital Control Systems Group
			Texas Instruments

Description:   This file contains source for the Full Compare BLDC PWM drivers for the F280x
              
Target: TMS320F280x family
              
=====================================================================================
History:
-------------------------------------------------------------------------------------
 04-15-2005	Version 3.20: Using DSP280x v. 1.10 or higher 
------------------------------------------------------------------------------------*/

#include "DSP280x_Device.h"
#include "f280xbldcpwm.h"

void F280X_BLDC_PWM_Init(PWMGEN *p) 
{       

         // Setup Sync
         EPwm1Regs.TBCTL.bit.SYNCOSEL = 0;          // Pass through
         EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;          // Pass through
         EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;          // Pass through
         EPwm4Regs.TBCTL.bit.SYNCOSEL = 0;          // Pass through
         EPwm5Regs.TBCTL.bit.SYNCOSEL = 0;          // Pass through
         EPwm6Regs.TBCTL.bit.SYNCOSEL = 0;          // Pass through

         // Allow each timer to be sync'ed
         EPwm1Regs.TBCTL.bit.PHSEN = 1;
         EPwm2Regs.TBCTL.bit.PHSEN = 1;
         EPwm3Regs.TBCTL.bit.PHSEN = 1;
         EPwm4Regs.TBCTL.bit.PHSEN = 1;
         EPwm5Regs.TBCTL.bit.PHSEN = 1;
         EPwm6Regs.TBCTL.bit.PHSEN = 1;

         // Init Timer-Base Period Register for EPWM1-EPWM3
         EPwm1Regs.TBPRD = p->PeriodMax;
         EPwm2Regs.TBPRD = p->PeriodMax;
         EPwm3Regs.TBPRD = p->PeriodMax;

         // Init Timer-Base Phase Register for EPWM1-EPWM3
         EPwm1Regs.TBPHS.half.TBPHS = 0;
         EPwm2Regs.TBPHS.half.TBPHS = 0;
         EPwm3Regs.TBPHS.half.TBPHS = 0;

         // Init Timer-Base Control Register for EPWM1-EPWM3
         EPwm1Regs.TBCTL.all = BLDCPWM_INIT_STATE;
         EPwm2Regs.TBCTL.all = BLDCPWM_INIT_STATE;
         EPwm3Regs.TBCTL.all = BLDCPWM_INIT_STATE;

         // Init Compare Control Register for EPWM1-EPWM3
         EPwm1Regs.CMPCTL.all = BLDCPWM_CMPCTL_INIT_STATE;
         EPwm2Regs.CMPCTL.all = BLDCPWM_CMPCTL_INIT_STATE;
         EPwm3Regs.CMPCTL.all = BLDCPWM_CMPCTL_INIT_STATE;

         // Init Action Qualifier Output A Register for EPWM1-EPWM3
         EPwm1Regs.AQCTLA.all = BLDCPWM_AQCTLA_INIT_STATE;
         EPwm2Regs.AQCTLA.all = BLDCPWM_AQCTLA_INIT_STATE;
         EPwm3Regs.AQCTLA.all = BLDCPWM_AQCTLA_INIT_STATE;

         // Init Dead-Band Generator Control Register for EPWM1-EPWM3
         EPwm1Regs.DBCTL.all = BLDCPWM_DBCTL_INIT_STATE;
         EPwm2Regs.DBCTL.all = BLDCPWM_DBCTL_INIT_STATE;
         EPwm3Regs.DBCTL.all = BLDCPWM_DBCTL_INIT_STATE;

         // Init PWM Chopper Control Register for EPWM1-EPWM3
         EPwm1Regs.PCCTL.all = BLDCPWM_PCCTL_INIT_STATE;
         EPwm2Regs.PCCTL.all = BLDCPWM_PCCTL_INIT_STATE;
         EPwm3Regs.PCCTL.all = BLDCPWM_PCCTL_INIT_STATE;
 
         EALLOW;                       // Enable EALLOW 

         // Init Trip Zone Select Register
         EPwm1Regs.TZSEL.all = BLDCPWM_TZSEL_INIT_STATE;
         EPwm2Regs.TZSEL.all = BLDCPWM_TZSEL_INIT_STATE;
         EPwm3Regs.TZSEL.all = BLDCPWM_TZSEL_INIT_STATE;

         // Init Trip Zone Control Register
         EPwm1Regs.TZCTL.all = BLDCPWM_TZCTL_INIT_STATE;
         EPwm2Regs.TZCTL.all = BLDCPWM_TZCTL_INIT_STATE;
         EPwm2Regs.TZCTL.all = BLDCPWM_TZCTL_INIT_STATE;

         // Setting six EPWM as primary output pins
         GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;   // EPWM1A pin
         GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;   // EPWM1B pin
         GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;   // EPWM2A pin
         GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;   // EPWM2B pin
         GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;   // EPWM3A pin
         GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;   // EPWM3B pin

         EDIS;                         // Disable EALLOW
}


void F280X_BLDC_PWM_Update(PWMGEN *p) 
{       

	int32 Tmp;
	int16 Period, GPR0_BLDC_PWM;

// Convert "Period" (Q15) modulation function to Q0
    Tmp = (int32)p->PeriodMax*(int32)p->MfuncPeriod;   // Q15 = Q0*Q15
    Period = (int16)(Tmp>>15);                         // Q15 -> Q0 (Period)
 
// Check PwmActive setting
	if (p->PwmActive==1)                   // PWM active high
      GPR0_BLDC_PWM = 0x7FFF - p->DutyFunc;   
    
    else if (p->PwmActive==0)              // PWM active low
      GPR0_BLDC_PWM = p->DutyFunc;

// Convert "DutyFunc" or "GPR0_BLDC_PWM" (Q15) duty modulation function to Q0
    Tmp = (int32)Period*(int32)GPR0_BLDC_PWM;     // Q15 = Q0*Q15

// State s1: current flows to motor windings from phase A->B, de-energized phase = C
	if (p->CmtnPointer==0)
    {
      EPwm1Regs.AQCSFRC.bit.CSFA = 0;       // Forcing disabledd on output A of EPWM1   
      EPwm1Regs.AQCTLA.bit.CAU = 2;         // Set high when CTR = CMPA on UP-count
      EPwm1Regs.AQCTLA.bit.ZRO = 1;         // Set low when CTR = Zero
      EPwm1Regs.CMPA.half.CMPA = (int16)(Tmp>>15); // PWM signal on output A of EPWM1 (Q15 -> Q0)  
      EPwm1Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM1   

      EPwm2Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM2   
      EPwm2Regs.AQCSFRC.bit.CSFB = 2;       // Forcing a continuous High on output B of EPWM2   

      EPwm3Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM3   
      EPwm3Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM3   
    }
    
// State s2: current flows to motor windings from phase A->C, de-energized phase = B
    else if (p->CmtnPointer==1)  
    {
      EPwm1Regs.AQCSFRC.bit.CSFA = 0;       // Forcing disabledd on output A of EPWM1   
      EPwm1Regs.AQCTLA.bit.CAU = 2;         // Set high when CTR = CMPA on UP-count
      EPwm1Regs.AQCTLA.bit.ZRO = 1;         // Set low when CTR = Zero
      EPwm1Regs.CMPA.half.CMPA = (int16)(Tmp>>15); // PWM signal on output A of EPWM1 (Q15 -> Q0)  
      EPwm1Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM1   

      EPwm2Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM2   
      EPwm2Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM2   

      EPwm3Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM3   
      EPwm3Regs.AQCSFRC.bit.CSFB = 2;       // Forcing a continuous High on output B of EPWM3   
    }

// State s3: current flows to motor windings from phase B->C, de-energized phase = A
    else if (p->CmtnPointer==2)  
    {
      EPwm1Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM1   
      EPwm1Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM1   

      EPwm2Regs.AQCSFRC.bit.CSFA = 0;       // Forcing disabled on output A of EPWM2   
      EPwm2Regs.AQCTLA.bit.CAU = 2;         // Set high when CTR = CMPA on UP-count
      EPwm2Regs.AQCTLA.bit.ZRO = 1;         // Set low when CTR = Zero
      EPwm2Regs.CMPA.half.CMPA = (int16)(Tmp>>15); // PWM signal on output A of EPWM2 (Q15 -> Q0)  
      EPwm2Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM2   

      EPwm3Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM3   
      EPwm3Regs.AQCSFRC.bit.CSFB = 2;       // Forcing a continuous High on output B of EPWM3   
    }
   
// State s4: current flows to motor windings from phase B->A, de-energized phase = C
    else if (p->CmtnPointer==3)  
    {
      EPwm1Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM1   
      EPwm1Regs.AQCSFRC.bit.CSFB = 2;       // Forcing a continuous High on output B of EPWM1   

      EPwm2Regs.AQCSFRC.bit.CSFA = 0;       // Forcing disabled on output A of EPWM2   
      EPwm2Regs.AQCTLA.bit.CAU = 2;         // Set high when CTR = CMPA on UP-count
      EPwm2Regs.AQCTLA.bit.ZRO = 1;         // Set low when CTR = Zero
      EPwm2Regs.CMPA.half.CMPA = (int16)(Tmp>>15); // PWM signal on output A of EPWM2 (Q15 -> Q0)  
      EPwm2Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM2   

      EPwm3Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM3   
      EPwm3Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM3   
    }

// State s5: current flows to motor windings from phase C->A, de-energized phase = B
    else if (p->CmtnPointer==4)  
    {
      EPwm1Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM1   
      EPwm1Regs.AQCSFRC.bit.CSFB = 2;       // Forcing a continuous High on output B of EPWM1   

      EPwm2Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM2   
      EPwm2Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM2   

      EPwm3Regs.AQCSFRC.bit.CSFA = 0;       // Forcing disabled on output A of EPWM3  
      EPwm3Regs.AQCTLA.bit.CAU = 2;         // Set high when CTR = CMPA on UP-count
      EPwm3Regs.AQCTLA.bit.ZRO = 1;         // Set low when CTR = Zero
      EPwm3Regs.CMPA.half.CMPA = (int16)(Tmp>>15); // PWM signal on output A of EPWM3 (Q15 -> Q0)  
      EPwm3Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM3   
    }

// State s6: current flows to motor windings from phase C->B, de-energized phase = A
    else if (p->CmtnPointer==5)  
    {
      EPwm1Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM1   
      EPwm1Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM1   

      EPwm2Regs.AQCSFRC.bit.CSFA = 1;       // Forcing a continuous Low on output A of EPWM2   
      EPwm2Regs.AQCSFRC.bit.CSFB = 2;       // Forcing a continuous High on output B of EPWM2   

      EPwm3Regs.AQCSFRC.bit.CSFA = 0;       // Forcing disabled on output A of EPWM3  
      EPwm3Regs.AQCTLA.bit.CAU = 2;         // Set high when CTR = CMPA on UP-count
      EPwm3Regs.AQCTLA.bit.ZRO = 1;         // Set low when CTR = Zero
      EPwm3Regs.CMPA.half.CMPA = (int16)(Tmp>>15); // PWM signal on output A of EPWM3 (Q15 -> Q0)  
      EPwm3Regs.AQCSFRC.bit.CSFB = 1;       // Forcing a continuous Low on output B of EPWM3   
    }

}