f280xbmsk.h

DSP280X芯片的编程简单例子

#define SOCASEL_DISABLE            0x0000
#define SOCASEL_ENABLE             0x0800

#define SOCBSEL_CNT_ZERO           0x1000
#define SOCBSEL_PRD_EQ             0x2000
#define SOCBSEL_CMPA_EQ_UC         0x4000
#define SOCBSEL_CMPA_EQ_DC         0x5000
#define SOCBSEL_CMPB_EQ_UC         0x6000
#define SOCBSEL_CMPB_EQ_DC         0x7000

#define SOCBSEL_DISABLE            0x0000
#define SOCBSEL_ENABLE             0x8000

/*------------------------------------------------------------------------------
 F280X Event Trigger Pre-Scale Register (ETPS)
------------------------------------------------------------------------------*/
#define INTPRD_DISABLE             0x0000
#define INTPRD_ONE_EVENT           0x0001
#define INTPRD_TWO_EVENT           0x0002
#define INTPRD_THREE_EVENT         0x0003

#define SOCAPRD_DISABLE            0x0000
#define SOCAPRD_ONE_EVENT          0x0100
#define SOCAPRD_TWO_EVENT          0x0200
#define SOCAPRD_THREE_EVENT        0x0300

#define SOCBPRD_DISABLE            0x0000
#define SOCBPRD_ONE_EVENT          0x1000
#define SOCBPRD_TWO_EVENT          0x2000
#define SOCBPRD_THREE_EVENT        0x3000

/*------------------------------------------------------------------------------
 F280X ECAP Control Register 1 (ECCTL1)
------------------------------------------------------------------------------*/
#define CAP1POL_RISING_EDGE        0x0000
#define CAP1POL_FALLING_EDGE       0x0001

#define CTRRST1_ABSOLUTE_TS        0x0000
#define CTRRST1_DIFFERENCE_TS      0x0002

#define CAP2POL_RISING_EDGE        0x0000
#define CAP2POL_FALLING_EDGE       0x0004

#define CTRRST2_ABSOLUTE_TS        0x0000
#define CTRRST2_DIFFERENCE_TS      0x0008

#define CAP3POL_RISING_EDGE        0x0000
#define CAP3POL_FALLING_EDGE       0x0010

#define CTRRST3_ABSOLUTE_TS        0x0000
#define CTRRST3_DIFFERENCE_TS      0x0020

#define CAP4POL_RISING_EDGE        0x0000
#define CAP4POL_FALLING_EDGE       0x0040

#define CTRRST4_ABSOLUTE_TS        0x0000
#define CTRRST4_DIFFERENCE_TS      0x0080

#define CAPLDEN_DISABLE            0x0000
#define CAPLDEN_ENABLE             0x0100

#define EVTFLTPS_X_1               0x0000
#define EVTFLTPS_X_2               0x0200
#define EVTFLTPS_X_4               0x0400
#define EVTFLTPS_X_6               0x0600
#define EVTFLTPS_X_8               0x0800
#define EVTFLTPS_X_10              0x0A00
#define EVTFLTPS_X_12              0x0C00
#define EVTFLTPS_X_14              0x0E00
#define EVTFLTPS_X_16              0x1000
#define EVTFLTPS_X_18              0x1200
#define EVTFLTPS_X_20              0x1400
#define EVTFLTPS_X_22              0x1600
#define EVTFLTPS_X_24              0x1800
#define EVTFLTPS_X_26              0x1A00
#define EVTFLTPS_X_28              0x1C00
#define EVTFLTPS_X_30              0x1E00
#define EVTFLTPS_X_32              0x2000
#define EVTFLTPS_X_34              0x2200
#define EVTFLTPS_X_36              0x2400
#define EVTFLTPS_X_38              0x2600
#define EVTFLTPS_X_40              0x2800
#define EVTFLTPS_X_42              0x2A00
#define EVTFLTPS_X_44              0x2C00
#define EVTFLTPS_X_46              0x2E00
#define EVTFLTPS_X_48              0x3000
#define EVTFLTPS_X_50              0x3200
#define EVTFLTPS_X_52              0x3400
#define EVTFLTPS_X_54              0x3600
#define EVTFLTPS_X_56              0x3800
#define EVTFLTPS_X_58              0x3A00
#define EVTFLTPS_X_60              0x3C00
#define EVTFLTPS_X_62              0x3E00

#define EMULATION_SOFT             0x0000
#define EMULATION_FREE             0x8000

/*------------------------------------------------------------------------------
 F280X ECAP Control Register 2 (ECCTL2)
------------------------------------------------------------------------------*/
#define CONTINUOUS_MODE           0x0000
#define ONE_SHOT_MODE             0x0001

#define ONESHT_CAP_EV1            0x0000
#define ONESHT_CAP_EV2            0x0002
#define ONESHT_CAP_EV3            0x0004
#define ONESHT_CAP_EV4            0x0006

#define TSCNTSTP_STOP             0x0000
#define TSCNTSTP_FREE             0x0010

#define SYNCI_DISABLE             0x0000
#define SYNCI_ENABLE              0x0020

#define SYNCO_SYNC_IN             0x0000
#define SYNCO_PRD_EQ              0x0040
#define SYNCO_DISABLE             0x0080

#define CAPTURE_MODE              0x0000
#define APWM_MODE                 0x0200

#define APWMPOL_HIGH              0x0000
#define APWMPOL_LOW               0x0400

/*------------------------------------------------------------------------------
 F280X EQEP Decode Control Register  (QDECCTL)
------------------------------------------------------------------------------*/
#define QSP_NO_EFFECT             0x0000
#define QSP_NEGATE                0x0020

#define QIP_NO_EFFECT             0x0000
#define QIP_NEGATE                0x0040

#define QBP_NO_EFFECT             0x0000
#define QBP_NEGATE                0x0080

#define QAP_NO_EFFECT             0x0000
#define QAP_NEGATE                0x0100

#define IGATE_DISABLE             0x0000
#define IGATE_WITH_STROBE         0x0200

#define SWAP_DISABLE              0x0000
#define SWAP_ENABLE               0x0400

#define XCR_X2                    0x0000
#define XCR_X1                    0x0800

#define SPSEL_INDEX               0x0000
#define SPSEL_STROBE              0x1000

#define SOEN_DISABLE              0x0000
#define SOEN_ENABLE               0x2000

#define QSRC_QUAD_MODE            0x0000
#define QSRC_DIR_MODE             0x4000
#define QSRC_UPCNT_MODE           0x8000
#define QSRC_DWNCNT_MODE          0xC000

/*------------------------------------------------------------------------------
 F280X EQEP Control Register  (QEPCTL)
------------------------------------------------------------------------------*/
#define WDE_DISABLE               0x0000
#define WDE_ENABLE                0x0001

#define UTE_DISABLE               0x0000
#define UTE_ENABLE                0x0002

#define QCLM_POSCNT               0x0000
#define QCLM_TIME_OUT             0x0004

#define QPEN_RESET                0x0000
#define QPEN_ENABLE               0x0008

#define IEL_RISING                0x0010
#define IEL_FALLING               0x0020
#define IEL_SOFTWARE              0x0030

#define SEL_RISING                0x0000
#define SEL_RISING_FALLING        0x0040

#define SWI_DISABLE               0x0000
#define SWI_POSCNT_INIT           0x0080

#define IEI_RISING                0x0200
#define IEI_FALLING               0x0300

#define SEI_RISING                0x0800
#define SEI_RISING_FALLING        0x0C00

#define PCRM_INDEX                0x0000
#define PCRM_POSMAX               0x1000
#define PCRM_FIRST_INDEX          0x2000
#define PCRM_TIME_EVENT           0x3000

#define QEP_EMULATION_SOFT        0x4000
#define QEP_EMULATION_FREE        0x8000

/*------------------------------------------------------------------------------
 F280X EQEP Position-Compare Control Register  (QPOSCTL)
------------------------------------------------------------------------------*/
#define PCE_DISABLE               0x0000
#define PCE_ENABLE                0x1000

#define PCPOL_HIGH                0x0000
#define PCPOL_LOW                 0x2000

#define PCLOAD_ZERO               0x0000
#define PCLOAD_QPOSCMP            0x4000

#define PCSHDW_DISABLE            0x0000
#define PCSHDW_ENABLE             0x8000

/*------------------------------------------------------------------------------
 F280X EQEP Capture Control Register  (QCAPCTL)
------------------------------------------------------------------------------*/
#define UPPS_X1                   0x0000
#define UPPS_X2                   0x0001
#define UPPS_X3                   0x0002
#define UPPS_X8                   0x0003
#define UPPS_X16                  0x0004
#define UPPS_X32                  0x0005
#define UPPS_X64                  0x0006
#define UPPS_X128                 0x0007
#define UPPS_X256                 0x0008
#define UPPS_X512                 0x0009
#define UPPS_X1024                0x000A
#define UPPS_X2048                0x000B

#define CCPS_X1                   0x0000
#define CCPS_X2                   0x0010
#define CCPS_X4                   0x0020
#define CCPS_X8                   0x0030
#define CCPS_X16                  0x0040
#define CCPS_X32                  0x0050
#define CCPS_X64                  0x0060
#define CCPS_X128                 0x0070

#define CEN_DISABLE               0x0000
#define CEN_ENABLE                0x8000

/*------------------------------------------------------------------------------
 F280X Register ADCTRL1
------------------------------------------------------------------------------*/
#define ADC_SUS_MODE0           0x0000
#define ADC_SUS_MODE1           0X1000
#define ADC_SUS_MODE2           0x2000
#define ADC_SUS_MODE3           0X3000
#define ADC_RESET_FLAG          0x4000

#define ADC_ACQ_PS_1            0x0000
#define ADC_ACQ_PS_2            0x0100
#define ADC_ACQ_PS_3            0x0200
#define ADC_ACQ_PS_4            0x0300
#define ADC_ACQ_PS_5            0x0400
#define ADC_ACQ_PS_6            0x0500
#define ADC_ACQ_PS_7            0x0600
#define ADC_ACQ_PS_8            0x0700
#define ADC_ACQ_PS_9            0x0800
#define ADC_ACQ_PS_10           0x0900
#define ADC_ACQ_PS_11           0x0A00
#define ADC_ACQ_PS_12           0x0B00
#define ADC_ACQ_PS_13           0x0C00
#define ADC_ACQ_PS_14           0x0D00
#define ADC_ACQ_PS_15           0x0E00
#define ADC_ACQ_PS_16           0x0F00

#define ADC_CPS_1               0x0000
#define ADC_CPS_2               0x0080
#define ADC_CONT_RUN            0x0040
#define ADC_SEQ_CASC            0x0010
#define ADC_SEQ_DUAL            0x0000

/*------------------------------------------------------------------------------
 F280X Register ADCTRL2
------------------------------------------------------------------------------*/
#define ADC_EPWM_SOCB           0x8000
#define ADC_RST_SEQ1            0x4000
#define ADC_SOC_SEQ1            0x2000

#define ADC_INT_ENA_SEQ1        0x0800
#define ADC_INT_MODE_SEQ1       0X0400
#define ADC_EPWM_SOCA_SEQ1      0x0100

#define ADC_EXT_SOC_SEQ1        0x0080
#define ADC_RST_SEQ2            0x0040
#define ADC_SOC_SEQ2            0x0020

#define ADC_INT_ENA_SEQ2        0x0008
#define ADC_INT_MODE_SEQ2       0x0004
#define ADC_EPWM_SOCB_SEQ2      0x0001

/*------------------------------------------------------------------------------
 F280X Register ADCTRL3
------------------------------------------------------------------------------*/
#define ADC_RFDN                0x0080
#define ADC_BGDN                0x0040
#define ADC_PWDN                0x0020

#define ADC_CLKPS_X_1           0x0000
#define ADC_CLKPS_X_2           0x0002
#define ADC_CLKPS_X_4           0x0004
#define ADC_CLKPS_X_6           0x0006
#define ADC_CLKPS_X_8           0x0008
#define ADC_CLKPS_X_10          0x000A
#define ADC_CLKPS_X_12          0x000C
#define ADC_CLKPS_X_14          0x000E
#define ADC_CLKPS_X_16          0x0010
#define ADC_CLKPS_X_18          0x0012
#define ADC_CLKPS_X_20          0x0014
#define ADC_CLKPS_X_22          0x0016
#define ADC_CLKPS_X_24          0x0018
#define ADC_CLKPS_X_26          0x001A
#define ADC_CLKPS_X_28          0x001C
#define ADC_CLKPS_X_30          0x001E

#define ADC_SMODE_SIMULTANEOUS  0x0001
#define ADC_SMODE_SEQUENTIAL    0x0000

#endif  // __F280X_BMSK_H__
// EOF