sdramcfg.s

CIRRUS 公司EP93XX系列CPU的WINCE下的BSP

;**********************************************************************
;                                                                      
; Filename: sdramcfg.s
;                                                                      
; Description: Configures SDRAM.
;
; THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
; ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
; PARTICULAR PURPOSE.
;
; Use of this source code is subject to the terms of the Cirrus end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to 
; use this source code. For a copy of the EULA, please see the 
; LICENSE.RTF on your install media.
;
; Copyright(c) Cirrus Logic Corporation 2002, All Rights Reserved                       
;                                                                      
;**********************************************************************

                OPT     2   ; disable listing
                OPT     1   ; reenable listing
                OPT     128 ; disable listing of macro expansions

GLOBALCFG_INIT              EQU         0x00000001
GLOBALCFG_MRS               EQU         0x00000002
GLOBALCFG_SMEMBUSY          EQU         0x00000020
GLOBALCFG_LCR               EQU         0x00000040
GLOBALCFG_REARBEN           EQU         0x00000080
GLOBALCFG_CLKSHUTDOWN       EQU         0x40000000
GLOBALCFG_CKE               EQU         0x80000000


REFRESH_MASK                EQU         0x0000FFFF

BOOTSTATUS_WIDTH_32         EQU         0x00000002
BOOTSTATUS_WIDTH_16         EQU         0x00000001
BOOTSTATUS_WIDTH_8          EQU         0x00000000
BOOTSTATUS_WIDTH_MASK       EQU         0x00000003
BOOTSTATUS_MEDIA            EQU         0x00000004

DEVCFG_EXTBUSWIDTH          EQU         0x00000004
DEVCFG_BANKCOUNT            EQU         0x00000008
DEVCFG_SROM512              EQU         0x00000010
DEVCFG_SROMLL               EQU         0x00000020
DEVCFG_2KPAGE               EQU         0x00000040
DEVCFG_SFCONFIGADDR         EQU         0x00000080
DEVCFG_CASLAT_MASK          EQU         0x00070000
DEVCFG_CASLAT_2             EQU         0x00010000
DEVCFG_CASLAT_3             EQU         0x00020000
DEVCFG_CASLAT_4             EQU         0x00030000
DEVCFG_CASLAT_5             EQU         0x00040000
DEVCFG_CASLAT_6             EQU         0x00050000
DEVCFG_CASLAT_7             EQU         0x00060000
DEVCFG_CASLAT_8             EQU         0x00070000
DEVCFG_WBL                  EQU         0x00080000
DEVCFG_RASTOCAS_MASK        EQU         0x00300000
DEVCFG_RASTOCAS_2           EQU         0x00200000
DEVCFG_RASTOCAS_3           EQU         0x00300000
DEVCFG_AUTOPRECHARGE        EQU         0x01000000

;****************************************************************************
; Delay200 - Delays200 us
;
;   Uses    r0
;****************************************************************************
                MACRO           
                Delay200
                mov             r0, #700
200             subs            r0, r0, #1
                bne             %b200
                MEND

;****************************************************************************
; Delay80 - Delays 80 Clocks
;
;
;   Uses    r0
;****************************************************************************
                MACRO           
                Delay80
                mov             r0, #80
80              subs            r0, r0, #1
                bne             %b80
                MEND


    AREA    |Assembly$$code|, CODE, READONLY 

;                TEXTAREA
                EXPORT          SdramCfg
;                LEAF_ENTRY      SdramCfg
SdramCfg
;
; Initialize the SDRAM Configuration
;
                ldr             r0, =(DEVCFG_BANKCOUNT :or: DEVCFG_SROMLL     :or: \
                                      DEVCFG_CASLAT_2  :or: DEVCFG_RASTOCAS_2 )
                ldr             r1, =0x8006001C
                str             r0, [r1]

                Delay200
;
; Set the Initialize and MRS bits (issue continuous NOP commands (INIT & MRS set))
;
                ldr             r0, =(GLOBALCFG_INIT :or: GLOBALCFG_MRS :or: \
                                      GLOBALCFG_CKE)
                ldr             r1, =0x80060004
                str             r0, [r1]

                Delay200

;
; Clear the MRS bit to issue a precharge all.
;
                ldr             r0, =(GLOBALCFG_INIT :or: GLOBALCFG_CKE)
                str             r0, [r1]

;
; Temporarily set the refresh timer to 0x10.  Make it really low so that auto refresh
; cycles are generated. is refreshed.
;
                ldr             r0, =0x10
                ldr             r1, =0x80060008
                str             r0, [r1]

                Delay80

                ldr             r0, =0x204
                ldr             r1, =0x80060008
                str             r0, [r1]

;
; Select mode register update mode
;
                ldr             r2, =(GLOBALCFG_CKE :or: GLOBALCFG_MRS)
                ldr             r1, =0x80060004
                str             r0, [r1]

; *******************************************************************
;
; Program the SDRAM mode register using the row information.
;
;       |           |           |           |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; |13|12|11|10|09|08|07|06|05|04|03|02|01|00|
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;   +---------+------+  +---+--+  +   +--+--+
;              |             |     |     |
;          Must Be Zero      |     |     |
;                            |     |     |
;                            |     |     |
;    LTMODE   ---------------+     |     |
;                                  |     |
;  Wrap type  ---------------------+     |
;                                        |
; CAS Latency ---------------------------+
;
; *******************************************************************
;
; Row Column mapping for 256Meg X 16 Bits X 2. SROM Look Alike mode
;
;           B1  B0  A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
;
; Row/Bank  A27 A26 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 
;
; Col       A27 A26             AP  A25 A24 A09 A08 A07 A06 A05 A04 A03 A02 
;
; *******************************************************************
; Sets all four banks using  - Cas latency 2
;                            - Wrap type sequential
;                            - Burst Length 4 
;
; *******************************************************************
                ldr             r1, =0x0008800
                ldr             r0, [r1]

                ldr             r1, =0x0408800
                ldr             r0, [r1]

                ldr             r1, =0x0808800
                ldr             r0, [r1]

                ldr             r1, =0x0C08800
                ldr             r0, [r1]


;
; Select mode register update mode
;
                ldr             r0, =GLOBALCFG_CKE
                ldr             r1, =0x80060004
                str             r0, [r1]
                mov             pc, lr

                END