📄 mmumap.c
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//**********************************************************************
//
// Filename: mmumap.c
//
// Description: This file contains a structure that help build the page
// table.
//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
// PARTICULAR PURPOSE.
//
// Use of this source code is subject to the terms of the Cirrus end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to
// use this source code. For a copy of the EULA, please see the
// EULA.RTF on your install media.
//
// Copyright(c) Cirrus Logic Corporation 2002, All Rights Reserved
//
//**********************************************************************
// OEMAddressTable defines the mapping from the 4GB physical address space
// to the kernel's 512MB "un-mapped" spaces. The kernel will create two ranges
// of virtual addresses from this table. One from 0x80000000 to 0x9FFFFFFF which
// has caching & buffering enabled and one from 0xA0000000 to 0xBFFFFFFF which
// has the cache & buffering disabled.
//
// WARNING: The above comments regarding address (0xA0000000) don't match our code.
//
//
// Each entry in the table consists of the Virtual Base Address to map to,
// the Physical Base Address to map from, and the number of megabytes to map.
//
// The order of the entries is arbitrary, but DRAM should be placed first for
// optimal performance. The table is zero-terminated, so the last entry MUST
// be all zeroes.
//
//
#include <memorymap.h>
#pragma data_seg(".astart")
typedef unsigned int ULONG;
typedef struct
{
ULONG ulVirtualAddress;
ULONG ulPhysicalAddress;
ULONG ulSizeInMegs;
} AddressTableStruct;
//
// Converts size in bytes to size in Megabytes rounded up.
//
#define MEG(A) (((A - 1)>>20) + 1)
const AddressTableStruct OEMAddressTable[] =
{
//
// SDRAM memory.
//
{
SDRAM_VIRTUAL_MEMORY,
PHYSICAL_ADDR_SDRAM_MAIN,
MEG(SDRAM_MAIN_BLOCK_SIZE)
},
{
SDRAM_VIRTUAL_MEMORY + SDRAM_MAIN_BLOCK_SIZE,
PHYSICAL_ADDR_SDRAM_MAIN + SDRAM_MAIN_BLOCK_SIZE + SDRAM_MAIN_SIZE_BETWEEN_BLOCKS,
MEG(SDRAM_MAIN_BLOCK_SIZE)
},
//
// Intel Flash Memory.
//
{
FLASH_VIRTUAL_MEMORY,
PHYSICAL_ADDR_FLASH_INTEL,
MEG(FLASH_SIZE)
},
////
//// The feature of 4-in-1 card support is removed from this BSP.
//// To add this feature, users need to sign related NDA's.
////
//#ifdef EP931X_MS_CARD
// //
// // Intel PHYSICAL_ADDR_ASYNC_CS7 Memory.
// //
// {
// MEM_HOST_REG_BASE_MS,
// PHYSICAL_ADDR_ASYNC_CS3,
// MEG(0x100)
// },
//#endif
//
//#ifdef EP931X_SD_MMC
//
// //
// // Intel PHYSICAL_ADDR_ASYNC_CS7 Memory.
// //
// {
// MEM_HOST_REG_BASE_SD_MMC,
// PHYSICAL_ADDR_ASYNC_CS7,
// MEG(0x100)
// },
//#endif
//
// Battery Backed SRAM.
//
{
SRAM_16BIT_VIRTUAL_MEMORY,
PHYSICAL_ADDR_SRAM_16BIT,
MEG(SIZE_SRAM_16BIT)
},
//
// System ASIC registers.
//
{
VIRTUAL_SYSTEM_ASIC_REGS_BASE,
PHYSICAL_SYSTEM_ASIC_REG_BASE,
MEG(SIZE_SYSTEM_ASIC_REG)
},
//
// PCMCIA memory windows.
//
{
PCMCIACARD_IO,
PCMCIACARD_IO_PHYSICAL,
MEG(PCMCIACARD_IO_SIZE)
},
{
PCMCIACARD_ATTRIBUTE,
PCMCIACARD_ATTRIBUTE_PHYSICAL,
MEG(PCMCIACARD_ATTRIBUTE_SIZE)
},
{
PCMCIACARD_MEMORY,
PCMCIACARD_MEMORY_PHYSICAL,
MEG(PCMCIACARD_MEMORY_SIZE)
},
//
// End of Table (MB MUST BE ZERO!)
//
{
0,
0,
0
}
};
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