oempreinit.c

CIRRUS 公司EP93XX系列CPU的WINCE下的BSP

//**********************************************************************
//                                                                      
// Filename: oempreinit.c
//                                                                      
// Description: This is the a routine that runs before turning on the
//              MMU.  Don't use any static data.
//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
// PARTICULAR PURPOSE.
//
// Use of this source code is subject to the terms of the Cirrus end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to 
// use this source code. For a copy of the EULA, please see the 
// EULA.RTF on your install media.
//
// Copyright(c) Cirrus Logic Corporation 2002, All Rights Reserved                       
//                                                                      
//**********************************************************************
//#pragma code_seg(".astart")
#ifndef PHYSICAL_EQUAL_VIRTUAL
#define PHYSICAL_EQUAL_VIRTUAL          1
#endif // PHYSICAL_EQUAL_VIRTUAL
#include <hwdefs.h>
#include <clocks.h>
typedef unsigned long ULONG;

//****************************************************************************
// SysconSetup
//****************************************************************************
// This sets up the syscon clock tree and the SMC timings. 
//
//
void SysconSetup()
{
    //
    // Disable the watchdog timer.
    //
    *WATCHDOG_WDCONTROL = WDCONTROL_DISABLE;

    //
    // According to the E28F128J3_150 specification. The timings are as follows:
    //
    // 150 ns    Memory access time.
    // 35  ns    Sequentail access time.
    // 1 HClock  Read to Write Turn around time
    //
    *SMC_SMCBCR6    = (( WAIT_STATES(35) <<SMCBCR_WST2_SHIFT) & SMCBCR_WST2_MASK) | 
                      (( WAIT_STATES(150) <<SMCBCR_WST1_SHIFT) & SMCBCR_WST1_MASK) |
                      ( 1 & SMCBCR_IDCY_MASK ) |  SMCBCR_MW_32BIT | SMCBCR_WP  |
                       SMCBCR_PME | SMCBCR_RBLE;


    //
    // Program the processor/bus clock rate.
    //
    *CSC_SYSLOCK = 0xAA;
    *CSC_CLKSET1 = CLKSET1_VALUE; 

    //
    // Flush the pipeline.
    //    
    __emit(0xe1a00000);
    __emit(0xe1a00000);
    __emit(0xe1a00000);
    __emit(0xe1a00000);
    __emit(0xe1a00000);
    __emit(0xe1a00000);

    //
    // Configure PLL2 in order to generate a solid 48Mhz clock for USB.
    //
    *CSC_SYSLOCK = 0xAA;
    *CSC_CLKSET2 = CLKSET2_VALUE; 

    //
    // Enable all of the UARTS and the math coprocessor.
    //
    *CSC_SYSLOCK =  0xAA;
    *CSC_DEVCFG  =  DEVCFG_U1EN  | DEVCFG_U2EN | DEVCFG_U3EN | DEVCFG_IONU2 | DEVCFG_TIN | 
                    DEVCFG_CPENA | DEVCFG_SHENA;

    //
    // Change the Bus master register to use bus priority 2 so that raster is stable.
    // This also puts dma at the top so audio does not break up.
    //
    *CSC_SYSLOCK =  0xAA;
    *CSC_BMAR    =  2;

    //
    // Program the sdram refresh to a new value.
    //
    *SDRAM_REFRESH = SDRAM_REFRESH_VALUE;

    //
    // Program the power control register to use all dma channels.
    //
    //ulPwrcnt = *CSC_PWRCNT;
    *CSC_SYSLOCK = 0xAA;
    *CSC_PWRCNT  = PWRCNT_DMAM2MCH0   | PWRCNT_DMAM2PCH1 | PWRCNT_DMAM2PCH0;

//                  PWRCNT_DMAM2PCH3 | PWRCNT_DMAM2PCH2 | PWRCNT_DMAM2PCH5 | 
//                  PWRCNT_DMAM2PCH4 | PWRCNT_DMAM2PCH7 | PWRCNT_DMAM2PCH6 |
//                  PWRCNT_DMAM2PCH9 | PWRCNT_DMAM2PCH8;

    //
    // Program up the SSP register.
    //
    *SPI_CPSR   = 2;


    //
    // Program the Touch Screen enable register.
    //
    *CSC_SYSLOCK    = 0xAA;
    *CSC_KTDIV      = KTDIV_TSEN;
 
}