csphy.h

CIRRUS 公司EP93XX系列CPU的WINCE下的BSP

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/************************************************************************
* BEGIN_MANUAL_ENTRY
*  Filename:    csPhy.h
*
*  Modification History:
*
*  5/30/2000 Melody Lee
*             Created the file  
*   
* END_MANUAL_ENTRY
*************************************************************************/
/* Csphy.h */

#ifndef _CSPHY_H_
#define _CSPHY_H_


/* PHY Registers */

/* All PHY's have the following seven registers */

#define PHYReg_BMCR     0x00    /* Basic Mode Control Register */
#define PHYReg_BMSR     0x01    /* Basic Mode Status Register */
#define PHYReg_PHYIDR1  0x02    /* PHY Identifier Register 1 */
#define PHYReg_PHYIDR2  0x03    /* PHY Identifier Register 2 */
#define PHYReg_ANAR     0x04    /* Auto-Negotiation Advertisement Register */
#define PHYReg_ANLPAR   0x05    /* Auto-Negotiation Link Partner Ability Reg */
#define PHYReg_ANER     0x06    /* Auto-Negotiation Expansion Register */


/*
*       PHYReg_BMCR     0x00    Basic Mode Control Register
*/
#define BMCR_Coll_Test          0x0080
#define BMCR_Full_Duplex        0x0100
#define BMCR_Restart_Auto_Neg   0x0200
#define BMCR_Isolate            0x0400
#define BMCR_Power_Down         0x0800
#define BMCR_Auto_Neg_Enable    0x1000
#define BMCR_100_MBPS           0x2000
#define BMCR_Loopback           0x4000
#define BMCR_Reset              0x8000


/*
*       PHYReg_BMSR     0x01    Basic Mode Status Register
*/
#define BMSR_Extended_Reg       0x0001
#define BMSR_Jabber             0x0002
#define BMSR_Valid_Link         0x0004
#define BMSR_Auto_Neg_Able      0x0008
#define BMSR_Remote_Fault       0x0010
#define BMSR_Auto_Neg_Complete  0x0020
#define BMSR_10BaseT_HDX_Able   0x0800
#define BMSR_10BaseT_FDX_Able   0x1000
#define BMSR_100BaseTX_HDX_Able 0x2000
#define BMSR_100BaseTX_FDX_Able 0x4000
#define BMSR_100BaseT4_Able     0x8000


/*
*       PHYReg_PHYIDR1  0x02    PHY Identifier Register 1
*       PHYReg_PHYIDR2  0x03    PHY Identifier Register 2
*/
#define PHYID_OUI_Mask          0x3FFFFC00
#define PHYID_Model_Mask        0x000003F0
#define PHYID_Revision_Mask     0x0000000F

#define PHYID_OUI_National      0x20005C00
#define PHYID_OUI_Crystal       0x001A2000
#define PHYID_OUI_ICS           0x0015F400

#define PHYID_Model_DP83840     0x00000000
#define PHYID_Model_CS8952      0x00000200
#define PHYID_Model_ICS1889     0x00000010
#define PHYID_Model_ICS1890     0x00000020

#define PHYID_Revision_A        0x00000001


/*
*       PHYReg_ANAR     0x04    Auto-Negotiation Advertisement Register
*/
#define ANAR_Tech_Ability_Mask  0x1FE0
#define ANAR_SeltField_IEEE8023 0x0001
#define ANAR_10BaseT_HDX_Able   0x0020
#define ANAR_10BaseT_FDX_Able   0x0040
#define ANAR_100BaseTX_HDX_Able 0x0080
#define ANAR_100BaseTX_FDX_Able 0x0100
#define ANAR_100BaseT4_Able     0x0200
#define ANAR_Pause_Able         0x0400
#define ANAR_Remote_Fault       0x2000
#define ANAR_Acknowledge        0x4000
#define ANAR_Next_Page          0x8000


/*
*       PHYReg_ANLPAR   0x05    Auto-Negotiation Link Partner Ability Reg
*/
#define ANLPAR_10BaseT_HDX_Able   0x0020
#define ANLPAR_10BaseT_FDX_Able   0x0040
#define ANLPAR_100BaseTX_HDX_Able 0x0080
#define ANLPAR_100BaseTX_FDX_Able 0x0100
#define ANLPAR_100BaseT4_Able     0x0200
#define ANLPAR_Pause_Able         0x0400
#define ANLPAR_Remote_Fault       0x2000
#define ANLPAR_Acknowledge        0x4000
#define ANLPAR_Next_Page          0x8000


/*
*       PHYReg_ANER     0x06    Auto-Negotiation Expansion Register
*/
#define ANER_LP_Auto_Neg_Able   0x0001
#define ANER_Page_Received      0x0002
#define ANER_Next_Page_Able     0x0004
#define ANER_LP_Next_Page_Able  0x0008
#define ANER_Parallel_Fault     0x0010


/*
*       PHYReg_PAR      0x19    PHY Address Register  (National Only)
*/
#define PHYReg_PAR              0x0019

#define PAR_PHY_Addr_Mask       0x001F
#define PAR_Unstable_Link       0x0020
#define PAR_10_Mbps             0x0040
#define PAR_Full_Duplex         0x0080  /* Rev A only */
#define PAR_FEFI_Enable         0x0100  /* Rev A only */
#define PAR_Tx_Delay            0x0200  /* Rev A only */
#define PAR_Auto_Neg_Enabled    0x0400  /* Rev A only */


/*
*       PHYReg_PCR      0x17    PCS Configuration Register  (National Only)
*/
#define PHYReg_PCR              0x0017

#define PCR_NRZI_EN             0x8000
#define PCR_Descr_To_Sel        0x4000
#define PCR_Descr_To_En         0x2000
#define PCR_Repeater            0x1000
#define PCR_Encsel              0x0800
#define PCR_Clk25MDis           0x0080
#define PCR_F_Link_100          0x0040
#define PCR_CIM_Dis             0x0020
#define PCR_Tx_Off              0x0010


/*
*       PHYReg_SSR      0x19    PHY Self Status Register  (Crystal Only)
*/
#define PHYReg_SSR              0x0019

#define SSR_PHY_Addr_Mask       0x001F
#define SSR_Unstable_Link       0x0020
#define SSR_10_Mbps             0x0040
#define SSR_Full_Duplex         0x0080
#define SSR_FEFI_Enable         0x0100
#define SSR_Pause_Enabled       0x0200
#define SSR_Auto_Neg_Enabled    0x0400
#define SSR_CRS_Disable         0x0800
#define SSR_Descrambler_Locked  0x1000
#define SSR_Receiving_Data      0x2000
#define SSR_Powered_Down        0x4000
#define SSR_Link_OK             0x8000


/*
*       PHYReg_QPR      0x11    PHY Quick Poll Register  (ICS Only)
*/
#define PHYReg_QPR              0x0011

#define QPR_Link_OK             0x0001
#define QPR_Remote_Fault        0x0002
#define QPR_Jabber              0x0004
#define QPR_Auto_Neg_Complete   0x0010
#define QPR_Premature_End       0x0020
#define QPR_Halt                0x0040
#define QPR_Invalid_Symbol      0x0080
#define QPR_False_Carrier       0x0100
#define QPR_PLL_Lock_Error      0x0200
#define QPR_Rx_Signal_Error     0x0400
#define QPR_Auto_Neg_Mask       0x3800
#define QPR_Full_Duplex         0x4000
#define QPR_100_Mbps            0x8000


#endif  /* _CSPHY_H_ */