📄 serial interface4.htm
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<H4>RS-232 receiver module</H4>Here's what we are trying to
build:<BR><BR><IMG
src="Serial Interface4.files/SerialRxDmodule.gif"><BR><BR>Our
implementation works like that:
<UL>
<LI>The module assembles data from the RxD line as it comes.
<LI>Once a complete byte has been received, it goes on the "data" bus,
and "data_ready" is asserted for one clock.
<LI>After that one clock, "data" should not be relied on anymore (as new
data may come that shuffles it). </LI></UL>
<H4>Oversampling</H4>An asynchronous receiver has to somehow get in-sync
on the incoming signal (it doesn't have access to the clock used during
transmission).
<UL>
<LI>To determine when a new data is coming ("start" bit), we oversample
the signal at a multiple of the baud rate frequency.
<LI>Once the "start" bit is detected, we sample the line at the baud
rate to acquire the data bits. </LI></UL>Receivers typically oversample
the incoming signal at 16 times the baud rate. Here we use 8 times. At
115200 bauds, that gives a sampling rate of 921600Hz.<BR><BR>Let's assume
that we have a "Baud8Tick" signal available, asserted 921600 times a
second.
<H4>The design</H4>First, the incoming "RxD" signal has no relationship
with our clock.<BR>We use two D-flipflops to synchronize it.
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<TD bgColor=#d0d0f0><B>reg</B> [1:0] RxD_sync;<BR><B>always</B>
@(<B>posedge</B> clk) <B>if</B>(Baud8Tick) RxD_sync <=
{RxD_sync_inv[0], RxD}; </TD></TR></TBODY></TABLE><BR>We filter the data,
so that short spikes on the RxD line aren't mistaken with start bits.
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<TD bgColor=#d0d0f0><B>reg</B> [1:0] RxD_cnt;<BR><B>reg</B>
RxD_bit;<BR><BR><B>always</B> @(<B>posedge</B>
clk)<BR><B>if</B>(Baud8Tick)<BR><B>begin</B><BR>
<B>if</B>(RxD_sync[1] && RxD_cnt!=2'b11) RxD_cnt <=
RxD_cnt + 1;<BR> <B>else</B> <BR> <B>if</B>(~RxD_sync[1]
&& RxD_cnt!=2'b00) RxD_cnt <= RxD_cnt - 1;<BR><BR>
<B>if</B>(RxD_cnt==2'b00) RxD_bit <= 0;<BR>
<B>else</B><BR> <B>if</B>(RxD_cnt==2'b11) RxD_bit <=
1;<BR><B>end</B> </TD></TR></TBODY></TABLE><BR>A state machine allows us
to go through each bit received, once a "start" is detected.
<TABLE cellPadding=10>
<TBODY>
<TR>
<TD bgColor=#d0d0f0><B>reg</B> [3:0] state;<BR><BR><B>always</B>
@(<B>posedge</B>
clk)<BR><B>if</B>(Baud8Tick)<BR><B>case</B>(state)<BR>
4'b0000: <B>if</B>(~RxD_bit) state <= 4'b1000; // start bit
found?<BR> 4'b1000: <B>if</B>(next_bit) state <= 4'b1001;
// bit 0<BR> 4'b1001: <B>if</B>(next_bit) state <= 4'b1010;
// bit 1<BR> 4'b1010: <B>if</B>(next_bit) state <= 4'b1011;
// bit 2<BR> 4'b1011: <B>if</B>(next_bit) state <= 4'b1100;
// bit 3<BR> 4'b1100: <B>if</B>(next_bit) state <= 4'b1101;
// bit 4<BR> 4'b1101: <B>if</B>(next_bit) state <= 4'b1110;
// bit 5<BR> 4'b1110: <B>if</B>(next_bit) state <= 4'b1111;
// bit 6<BR> 4'b1111: <B>if</B>(next_bit) state <= 4'b0001;
// bit 7<BR> 4'b0001: <B>if</B>(next_bit) state <= 4'b0000;
// stop bit<BR> default: state <=
4'b0000;<BR><B>endcase</B> </TD></TR></TBODY></TABLE><BR>Notice that we
used a "next_bit" signal, to go from bit to bit.
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<TD bgColor=#d0d0f0><B>reg</B> [2:0]
bit_spacing;<BR><BR><B>always</B> @(<B>posedge</B>
clk)<BR><B>if</B>(state==0)<BR> bit_spacing <=
0;<BR><B>else</B><BR><B>if</B>(Baud8Tick)<BR> bit_spacing
<= bit_spacing + 1;<BR><BR><B>wire</B> next_bit =
(bit_spacing==7); </TD></TR></TBODY></TABLE><BR>Finally a shift register
collects the data bits as they come.
<TABLE cellPadding=10>
<TBODY>
<TR>
<TD bgColor=#d0d0f0><B>reg</B> [7:0] RxD_data;<BR><B>always</B>
@(<B>posedge</B> clk) <B>if</B>(Baud8Tick && next_bit
&& state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
</TD></TR></TBODY></TABLE><BR>That's it! The complete code can be found <A
href="http://www.fpga4fun.com/files/async.zip">here</A>.<BR>It has a few
improvements; follow the comments in the code.
<H4>Links</H4>
<UL>
<LI>More details on <A
href="http://www.erg.abdn.ac.uk/users/gorry/course/phy-pages/async.html">Asynchronous
Communication</A> </LI></UL><BR><BR><A
href="http://www.fpga4fun.com/SerialInterface5.html"><FONT color=blue
size=2>>>> NEXT: How to use the Transmitter and Receiver modules
>>></FONT></A><BR><BR><BR>
<HR>
This page was last updated on May 10
2004.<BR><BR></TD></TR></TBODY></TABLE></BODY></HTML>
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