📄 serial interface3.htm
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<H4>RS-232 transmitter module</H4>Here's what we are trying to
build:<BR><BR><IMG
src="Serial Interface3.files/SerialTxDmodule.gif"><BR><BR>It works like
that:
<UL>
<LI>The transmitter takes an 8-bits data, and serializes it (starting
when the "TxD_start" signal is asserted).
<LI>The "busy" signal is asserted while a transmission occurs. The
"TxD_start" signal is ignored during that time. </LI></UL>The RS-232
parameters used are fixed: 8-bits data, 2 stop bits, no-parity.
<H4>Serializing the data</H4>We assume that we have a "BaudTick" signal
available, asserted 115200 times a second.<BR><BR>We need to generate the
start bit, the 8 data bits, and the stop bits.<BR>A state machine seems
appropriate.<BR><BR>
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<TD bgColor=#d0d0f0><B>reg</B> [3:0] state;<BR><BR><B>always</B>
@(<B>posedge</B> clk)<BR><B>case</B>(state)<BR> 4'b0000:
<B>if</B>(TxD_start) state <= 4'b0100;<BR> 4'b0100:
<B>if</B>(BaudTick) state <= 4'b1000; // start<BR> 4'b1000:
<B>if</B>(BaudTick) state <= 4'b1001; // bit 0<BR> 4'b1001:
<B>if</B>(BaudTick) state <= 4'b1010; // bit 1<BR> 4'b1010:
<B>if</B>(BaudTick) state <= 4'b1011; // bit 2<BR> 4'b1011:
<B>if</B>(BaudTick) state <= 4'b1100; // bit 3<BR> 4'b1100:
<B>if</B>(BaudTick) state <= 4'b1101; // bit 4<BR> 4'b1101:
<B>if</B>(BaudTick) state <= 4'b1110; // bit 5<BR> 4'b1110:
<B>if</B>(BaudTick) state <= 4'b1111; // bit 6<BR> 4'b1111:
<B>if</B>(BaudTick) state <= 4'b0001; // bit 7<BR> 4'b0001:
<B>if</B>(BaudTick) state <= 4'b0010; // stop1<BR> 4'b0010:
<B>if</B>(BaudTick) state <= 4'b0000; // stop2<BR> default:
<B>if</B>(BaudTick) state <= 4'b0000;<BR><B>endcase</B>
</TD></TR></TBODY></TABLE><BR>Notice how the state machine starts right
when "TxD_start" is asserted, but then only advances when "BaudTick" is
asserted.<BR><BR>Now, we just need to generate the "TxD" output.<BR>
<TABLE cellPadding=10>
<TBODY>
<TR>
<TD bgColor=#d0d0f0><B>reg</B> muxbit;<BR><BR><B>always</B>
@(state[2:0])<BR><B>case</B>(state[2:0])<BR> 0: muxbit <=
TxD_data[0];<BR> 1: muxbit <= TxD_data[1];<BR> 2:
muxbit <= TxD_data[2];<BR> 3: muxbit <=
TxD_data[3];<BR> 4: muxbit <= TxD_data[4];<BR> 5:
muxbit <= TxD_data[5];<BR> 6: muxbit <=
TxD_data[6];<BR> 7: muxbit <=
TxD_data[7];<BR><B>endcase</B><BR><BR>// combine start, data, and
stop bits together<BR><B>assign</B> TxD = (state<4) | (state[3]
& muxbit); </TD></TR></TBODY></TABLE><BR>Notice that the "TxD_data"
input needs to stay stable while the character is being sent. Keep that in
mind when you use this module. You could also modify this module to
register internally "TxD_data" when transmission starts.<BR><BR>That's it!
The complete code can be found <A
href="http://www.fpga4fun.com/files/async.zip">here</A>. <BR><BR><A
href="http://www.fpga4fun.com/SerialInterface4.html"><FONT color=blue
size=2>>>> NEXT: RS-232 receiver module
>>></FONT></A><BR><BR><BR>
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This page was last updated on May 22
2004.<BR><BR></TD></TR></TBODY></TABLE></BODY></HTML>
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