📄 serial interface2.htm
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<TD bgColor=#9090c0 vAlign=top><FONT size=40>fpga4fun.com</FONT> - where
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<H4>Baud generator</H4>Here we want to use the serial link at maximum
speed, i.e. 115200 bauds. Other slower speeds would also be easy to
generate.<BR><BR>FPGAs usually run at speed well above 115200Hz (RS-232 is
pretty slow by today's standards). That means we use a high-speed clock
and divide it down to generate a "tick" as close as possible to 115200
times a second.
<H4>Synchronous tick from a 1.8432MHz clock</H4>Traditionally, RS-232
chips use a 1.8432MHz clock, because that makes generating the standard
baud frequencies very easy. So let's assume we have a 1.8432MHz clock
available.<BR><BR>1.8432MHz divided by 16 gives 115200Hz, what a
coincidence!<BR><BR>
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<TD bgColor=#d0d0f0><B>reg</B> [3:0] BaudDivCnt;<BR><B>always</B>
@(<B>posedge</B> clk) BaudDivCnt <= BaudDivCnt +
1;<BR><BR><B>wire</B> BaudTick = (BaudDivCnt==15);
</TD></TR></TBODY></TABLE><BR>So "BaudTick" is asserted once every 16
clocks, i.e. 115200 times a second when using a 1.8432MHz clock.
<H4>Synchronous tick from any frequency</H4>The earlier generator was
assuming the use of a 1.8432MHz clock. But what do you do if all your have
is, say, a 2MHz clock? To generate 115200Hz from a 2MHz clock, you divide
the clock by "17.361111111..." Not exactly a round number. The solution is
to divide sometimes by 17, sometimes by 18, making sure the ratio stays
"17.361111111". That's actually easy to do.<BR><BR>Look at the following
"C" code:<BR>
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<TD bgColor=#d0d0f0>while(1) // repeat forever<BR>{<BR> acc +=
115200;<BR> if(acc>=2000000) printf("*"); else printf("
");<BR><BR> acc %=
2000000;<BR>}<BR></TD></TR></TBODY></TABLE><BR>That prints the "*" in the
exact ratio, once every "17.361111111..." loops on average.<BR><BR>To
obtain the same thing efficiently in an FPGA, we rely on the fact that the
serial interface can tolerate a few % of error in the baud frequency
generator. It really won't matter if we use "17.3" or "17.4".
<H4>FPGA baud generator</H4>It is desirable that the 2000000 be a power of
two. Obviously 2000000 is not a power of two. So we change the ratio.
Instead of the ratio "2000000/115200", let's use "1024/59" = 17.356.
That's very close to our ideal ratio, and makes an efficient FPGA
implementation.<BR><BR>
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<TD bgColor=#d0d0f0>// 10 bits for the accumulator ([9:0]), and one
extra bit for the accumulator carry-out ([10])<BR><B>reg</B> [10:0]
acc; // 11 bits total!<BR><BR><B>always</B> @(<B>posedge</B>
clk)<BR> acc <= acc[9:0] + 59; // use only 10 bits from the
previous result, but save the full 11 bits<BR><BR><B>wire</B>
BaudTick = acc[10]; // so that the 11th bit is the carry-out
</TD></TR></TBODY></TABLE><BR>Using out 2MHz clock, "BaudTick" is asserted
115234 times a second, a 0.03% error from the ideal 115200.
<H4>Parameterized FPGA baud generator</H4>The previous design was using a
10 bits accumulator, but as the clock frequency increases, more bits are
required.<BR><BR>Here's a design with a 25MHz clock and a 16 bits
accumulator. The design is parameterized, so easy to customize.<BR><BR>
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<TD bgColor=#d0d0f0><B>parameter</B> ClkFrequency = 25000000; //
25MHz<BR><B>parameter</B> Baud = 115200;<BR><B>parameter</B>
BaudGeneratorAccWidth = 16;<BR><B>parameter</B> BaudGeneratorInc =
(Baud<<BaudGeneratorAccWidth)/ClkFrequency;<BR><BR><B>reg</B>
[BaudGeneratorAccWidth:0] BaudGeneratorAcc;<BR><B>always</B>
@(<B>posedge</B> clk)<BR> BaudGeneratorAcc <=
BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] +
BaudGeneratorInc;<BR><BR><B>wire</B> BaudTick =
BaudGeneratorAcc[BaudGeneratorAccWidth]; </TD></TR></TBODY></TABLE><BR>One
last implementation issue: the "BaudGeneratorInc" calculation is wrong,
due to the fact that Verilog uses 32 bits intermediate results, and the
calculation exceeds that. Change the line as follow for a
workaround.<BR><BR>
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<TD bgColor=#d0d0f0><B>parameter</B> BaudGeneratorInc =
((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
</TD></TR></TBODY></TABLE><BR>This line has also the added advantage to
round the result instead of truncating.<BR><BR>That's it.<BR>Now that we
have a precise enough Baud generator, we can go ahead with the RS-232
transmitter and receiver modules. <BR><BR><A
href="http://www.fpga4fun.com/SerialInterface3.html"><FONT color=blue
size=2>>>> NEXT: RS-232 transmitter module
>>></FONT></A><BR><BR><BR>
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This page was last updated on May 22
2004.<BR><BR></TD></TR></TBODY></TABLE></BODY></HTML>
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