smsc83c180.h

基于嵌入式操作系统VxWorks的lan91c111的驱动程序

/* smsc83c180.h - SMSC LAN83C180  */ 

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01a, 14Oct02, s_m mostly copied from if_fsmc.h 
*/

/* Read-Write PHY */

#define ESMC_PHY_OPWrite       0x01    /* Write PHY */
#define ESMC_PHY_OPRead        0x02    /* Read PHY */

/* PHY Register Numbers */
/*
 * PHY registers 0 and 1 are mandatory, 2-7 are optional, 8-15 are reserved and
 * 16-31 are vendor proprietary. 
*/

#define PHY_CONTROL            0x0     /* Control Register */
#define PHY_STATUS             0x1     /* Status Register */
#define PHY_ID1                0X2     /* ID1 Register */
#define PHY_ID2                0X3     /* ID2 Register */
#define PHY_AUTO_AD            0x4     /* Auto-Negotiation Advertisement Register */
#define PHY_AUTO_LINK          0x5     /* Auto-Negotiation Link Partner Register */
#define PHY_AUTO_EXP           0x6     /* Auto-Negotiation Expansion */
#define PHY_AUTO_NXT_PAGE_XMT  0x7     /* Auto-Neg. Next Page Xmit Register */
#define PHY_RES8               0x8     /* Reserved Register */ 
#define PHY_RES9               0x9     /* Reserved Register */ 
#define PHY_RES10              0xA     /* Reserved Register */ 
#define PHY_RES11              0xB     /* Reserved Register */ 
#define PHY_RES12              0xC     /* Reserved Register */ 
#define PHY_RES13              0xD     /* Reserved Register */ 
#define PHY_RES14              0xE     /* Reserved Register */ 
#define PHY_RES15              0xF     /* Reserved Register */ 
#define PHY_RES16              0x10    /* Reserved Register */ 
#define PHY_RES17              0x11    /* Reserved Register */ 
#define PHY_DCR                0x12    /* Disconnect Counter Register */ 
#define PHY_FCSCR              0x13    /* False Carrier Sense Counter Reg */ 
#define PHY_RES20              0x14    /* Reserved Register (DO NOT R/W) */ 
#define PHY_RECR               0x15    /* Receive Error Counter Reg */ 
#define PHY_SRR                0x16    /* Silicon Revision Register */
#define PHY_PCR                0x17    /* PCS Sub-Layer Configuration Reg */
#define PHY_LBREMR             0x18    /* Loopback, Bypass & Receiver Error Mask Reg */
#define PHY_PAR                0x19    /* PHY Address Register */
#define PHY_VENDOR26           0x1A    /* Vendor Proprietary Register */
#define PHY_10BTSR             0x1B    /* 10BaseT Status Register */
#define PHY_10BTCR             0x1C    /* 10BaseT Configuration Register */
#define PHY_VENDOR29           0x1D    /* Vendor Proprietary Register  */
#define PHY_VENDOR30           0x1E    /* Vendor Proprietary Register  */
#define PHY_VENDOR31           0x1F    /* Vendor Proprietary Register  */

#define PHY_SMSC83C180_ID1      0x0282
#define PHY_SMSC83C180_ID2      0x1C00  /* the lowest byte can vary */

/* PHY Control Register Definition */

#define PHY_CTRL_COLTST        0x0080  /* Col Test Bit */
#define PHY_CTRL_DUPLEX        0x0100  /* Duplex Mode Bit */
#define PHY_CTRL_NWAYREST      0x0200  /* NWAY REST Bit */
#define PHY_CTRL_ISOLATE       0x0400  /* Isolation Bit */
#define PHY_CTRL_PWRDOWN       0x0800  /* PHY Power Down Bit */
#define PHY_CTRL_NWAYEN        0x1000  /* Auto-Negotiation Enable Bit */
#define PHY_CTRL_SPEED         0x2000  /* 10 or 100 Mbps Speed Bit (manual prog.) */
#define PHY_CTRL_LOOPBACK      0x4000  /* Loopback Bit */
#define PHY_CTRL_RESET         0x8000  /* Reset Bit */

/* PHY Status Register Definition */

#define PHY_STAT_EXTEND_CAP    0x0001  /* Extended Register Capability Bit */
#define PHY_STAT_JABBER_DET    0x0002  /* Jabber Condition Detected Bit */
#define PHY_STAT_LNK_STAT      0x0004  /* Valid Link Bit */
#define PHY_STAT_NWAY_AVAIL    0x0008  /* Auto-Negotiation Capability Bit */
#define PHY_STAT_REM_FAULT     0x0010  /* Remote Fault Bit */
#define PHY_STAT_NWAY_COMP     0x0020  /* Auto-Negotiation Complete Bit */
#define PHY_STAT_MPRE_SUP      0x0040  /* MF Preample Suppression Bit */
#define PHY_STAT_10BPSH        0x0800  /* 10 Mbps Half Duplex Capability Bit */
#define PHY_STAT_10BPSD        0x1000  /* 10 Mbps Full Duplex Capability Bit */
#define PHY_STAT_100BASEXH     0x2000  /* 100 BaseXH Half Duplex Capability Bit */
#define PHY_STAT_100BASEXD     0x4000  /* 100 BaseXD Full Duplex Capability Bit */
#define PHY_STAT_100BASET4     0x5000  /* 100 BaseT4 Capability Bit */

/* PHY Auto-Negotiation Advertisement Register Definition */

#define PHY_AUTO_AD_S0          0x0001  /* Selector Field 0 Bit */
#define PHY_AUTO_AD_S1          0x0002  /* Selector Field 1 Bit */
#define PHY_AUTO_AD_S2          0x0004  /* Selector Field 2 Bit */
#define PHY_AUTO_AD_S3          0x0008  /* Selector Field 3 Bit */
#define PHY_AUTO_AD_S4          0x0010  /* Selector Field 4 Bit */
#define PHY_AUTO_AD_TA0         0x0020  /* 10 BaseT Capability Bit */
#define PHY_AUTO_AD_TA1         0x0040  /* 10 BaseT Full Duplex Capability Bit */
#define PHY_AUTO_AD_TA2         0x0080  /* 100 BaseTX Capability Bit */
#define PHY_AUTO_AD_TA3         0x0100  /* 100 BaseTX Full Duplex Capability Bit */
#define PHY_AUTO_AD_TA4         0x0200  /* 100 BaseT4 Capability Bit */
#define PHY_AUTO_AD_TA5         0x0400  /* Technology Ability 5 Bit */
#define PHY_AUTO_AD_TA6         0x0800  /* Technology Ability 6 Bit */
#define PHY_AUTO_AD_TA7         0x1000  /* Technology Ability 7 Bit */
#define PHY_AUTO_AD_REMFAULT    0x2000  /* Remote Fault Bit */
#define PHY_AUTO_AD_ACK         0x4000  /* Acknowledge Bit */
#define PHY_AUTO_AD_NXTPAGE     0x8000  /* Exchange Next Page Information Bit */

/* PHY Auto-Negotiation Link Partner Ability Register Definition */

#define PHY_AUTO_LINK_S0        0x0001  /* Selector Field 0 Bit */
#define PHY_AUTO_LINK_S1        0x0002  /* Selector Field 1 Bit */
#define PHY_AUTO_LINK_S2        0x0004  /* Selector Field 2 Bit */
#define PHY_AUTO_LINK_S3        0x0008  /* Selector Field 3 Bit */
#define PHY_AUTO_LINK_S4        0x0010  /* Selector Field 4 Bit */
#define PHY_AUTO_LINK_10BT      0x0020  /* 10 BaseT Capability Bit */
#define PHY_AUTO_LINK_10BTF     0x0040  /* 10 BaseT Full Duplex Capability Bit */
#define PHY_AUTO_LINK_100BTX    0x0080  /* 100 BaseTX Capability Bit */
#define PHY_AUTO_LINK_100BTXF   0x0100  /* 100 BaseTX Full Duplex Capability Bit */
#define PHY_AUTO_LINK_100BT4    0x0200  /* 100 BaseT4 Capability Bit */
#define PHY_AUTO_LINK_RES10     0x0400  /* Reserved Bit */
#define PHY_AUTO_LINK_RES11     0x0800  /* Reserved Bit */
#define PHY_AUTO_LINK_RES12     0x1000  /* Reserved Bit */
#define PHY_AUTO_LINK_REMFAULT  0x2000  /* Remote Fault Bit */
#define PHY_AUTO_LINK_ACK       0x4000  /* Received Partner Link Code Word Bit */
#define PHY_AUTO_LINK_NXTPAGE   0x8000  /* Exchange Next Page Information Bit */

/* PHY Auto-Negotiation Expansion Register Definition */

#define PHY_AUTO_EXP_RES1       0x0001  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES2       0x0002  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES3       0x0004  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES4       0x0008  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES5       0x0010  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES6       0x0020  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES7       0x0040  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES8       0x0080  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES9       0x0100  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES10      0x0200  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_RES11      0x0400  /* ANER Reserved Bit */
#define PHY_AUTO_EXP_MLF        0x0800  /* Mulitple Link Fault Bit */
#define PHY_AUTO_EXP_LP_NP_ABLE 0x1000  /* Link Partner Next Page Able Bit */
#define PHY_AUTO_EXP_NP_ABLE    0x2000  /* Next Page Able Bit */
#define PHY_AUTO_EXP_PAGE_RX    0x4000  /* Link Code Word Page Received Bit */
#define PHY_AUTO_EXP_LP_AN_ABLE 0x8000  /* Link Partner Auto-Negotiation Able Bit */

/* PCS Configuration Register(PCR) Definition */

#define PHY_PCR_NRZI_EN         0x0001  /* NRZI Enable */
#define PHY_PCR_DESCR_TO_SEL    0x0002  /* Descramble Timeout Select */
#define PHY_PCR_DESCR_TO_DIS    0x0004  /* Descramble Timeout Disable */
#define PHY_PCR_REPEATER        0x0008  /* Repeater/Node Mode */
#define PHY_PCR_ENCSEL          0x0010  /* Encoder Mode Select */
#define PHY_PCR_RES6            0x0020  /* PCR Reserved Bit */
#define PHY_PCR_RES7            0x0040  /* PCR Reserved Bit */
#define PHY_PCR_RES8            0x0080  /* PCR Reserved Bit */
#define PHY_PCR_CLK25MDIS       0x0100  /* CLK25M Disable */
#define PHY_PCR_F_LINK_100      0x0200  /* Force Good Link in 100Mbps */
#define PHY_PCR_CIM_DIS         0x0400  /* Carrier Integrity Monitor Disable */
#define PHY_PCR_TX_OFF          0x0800  /* Force Transmit Off */
#define PHY_PCR_RES13           0x1000  /* PCR Reserved Bit */
#define PHY_PCR_LED1_MODE       0x2000  /* LED1_Mode */
#define PHY_PCR_LED4_MODE       0x4000  /* LED4_Mode */
#define PHY_PCR_RES16           0x8000  /* PCR reserved Bit */

/* Loopback, BYPASS and Receiver Error Mask Register(LBREMR) Definition */

#define PHY_LBREMR_RES0         0x0001  /* LBREMR Reserved Bit */
#define PHY_LBREMR_PKT_ERR      0x0002  /* Packet Errors */
#define PHY_LBREMR_LINK_ERR     0x0004  /* Link Errors */
#define PHY_LBREMR_PE_ERR       0x0008  /* Premature End Errors */
#define PHY_LBREMR_CODE_ERR     0x0010  /* Code Errors */
#define PHY_LBREMR_LBK_XMT_DS   0x0020  /* 100Mb/s Xmit Disable in Loopback */
#define PHY_LBREMR_ALT_CRS      0x0040  /* Alternate CRS Operation */
#define PHY_LBREMR_RES7         0x0080  /* LBREMR Reserved Bit */
#define PHY_LBREMR_LB0          0x0100  /* Loopback Control Bit 0 */
#define PHY_LBREMR_LB1          0x0200  /* Loopback Control Bit 1 */
#define PHY_LBREMR_RES10        0x0400  /* LBREMR Reserved Bit */
#define PHY_LBREMR_10BT_LPBK    0x0800  /* 10BaseT Encoder/Decoder Loopback*/
#define PHY_LBREMR_BP_ALIGN     0x1000  /* BYPASS Symbol Alignment Function */
#define PHY_LBREMR_BP_SCR       0x2000  /* BYPASS Scrambler/Descrambler Function */
#define PHY_LBREMR_BP_4B5B      0x4000  /* BYPASS 4B5B Encoding/Decoding */
#define PHY_LBREMR_BAD_SSD_EN   0x8000  /* Bad SSD Enable */

/* PHY Address Register(PAR) Definition */

#define PHY_PAR_PHYADDR0        0x0001  /**/
#define PHY_PAR_PHYADDR1        0x0002  /*  */
#define PHY_PAR_PHYADDR2        0x0004  /* */
#define PHY_PAR_PHYADDR3        0x0008  /*  */
#define PHY_PAR_PHYADDR4        0x0010  /*  */
#define PHY_PAR_CIM_STATUS      0x0020  /*  */
#define PHY_PAR_SPEED_10        0x0040  /* */
#define PHY_PAR_DUPLEX_STAT     0x0080  /*  */
#define PHY_PAR_FEFI_EN         0x0100  /* */
#define PHY_PAR_RES9            0x0200  /* */
#define PHY_PAR_AN_EN_STAT      0x0400  /* */
#define PHY_PAR_DIS_CRS_JAB     0x0800  /*  */
#define PHY_PAR_RES12           0x1000  /* */
#define PHY_PAR_RES13           0x2000  /* */
#define PHY_PAR_RES14           0x4000  /*  */
#define PHY_PAR_RES15           0x8000  /*  */