esmcend.h

基于嵌入式操作系统VxWorks的lan91c111的驱动程序

#define ESMC_CFG_NO_WAIT_ST   0x1000    /* when set */
/* unused                     0x2000     */
/* unused                     0x4000     */
/* unused                     0x8000     */


#define ESMC_INT_INTR_ZERO    0xf9    /* mask to clear interrrupt setting */
#define ESMC_INT_SEL_INTR0    0x0
#define ESMC_INT_SEL_INTR1    0x2
#define ESMC_INT_SEL_INTR2    0x4
#define ESMC_INT_SEL_INTR3    0x6    

/* Control Register */
#define ESMC_CTR_STORE           0x0001
#define ESMC_CTR_RELOAD          0x0002
#define ESMC_CTR_EPROM_SELECT    0x0004    /* EEprom access bit */
/* unused                        0x0008     */

/* unused                        0x0010     */
#define    ESMC_CTR_TE_ENABLE    0x0020    /* transmit error enable */
#define    ESMC_CTR_CR_ENABLE    0x0040    /* counter rollover enable */
#define    ESMC_CTR_LE_ENABLE    0x0080    /* Link error enable */

/* unused                        0x0100     */
/* unused                        0x0200     */
/* unused                        0x0400     */
#define ESMC_CTR_AUTO_RELEASE    0x0800    /* transmit memory auto released */

/* unused                        0x1000     */
#define ESMC_CTR_PWEDN           0x2000    /* high puts chip in powerdown mode */
#define ESMC_CTR_RCV_BAD         0x4000    /* when set bad CRC packets received */
/* unused                        0x8000     */


/* BANK 2 I/O Space mapping */
#ifndef SH_BIG_ENDIAN
#define ESMC_MMU                0x0    /* MMU command register */
#define ESMC_PNR                0x2    /* packet number register */ 
#define ESMC_FIFO               0x4    /* FIFO ports register */
#define ESMC_PTR                0x6    /* pointer register */
#define ESMC_DATA_1             0x8    /* data register 1 */
#define ESMC_DATA_2             0xA    /* data register 2 */
#define ESMC_INTERRUPT_         0xC    /* int status & acknowledge register */
#else
#define ESMC_MMU                0x2    /* MMU command register */
#define ESMC_PNR                0x0    /* packet number register */ 
#define ESMC_FIFO               0x6    /* FIFO ports register */
#define ESMC_PTR                0x4    /* pointer register */
#define ESMC_DATA_1             0xA    /* data register 1 */
#define ESMC_DATA_2             0x8    /* data register 2 */
#define ESMC_INTERRUPT_         0xE    /* int status & acknowledge register */
#endif /* SH_BIG_ENDIAN */

/* MMU Command Register */
#define ESMC_MMU_BUSY           0x0001    /* set if MMU busy */
#define ESMC_MMU_N0             0x0001
#define ESMC_MMU_N1             0x0002
#define ESMC_MMU_N2             0x0004
/* unused                       0x0008     */
/* unused                       0x0010     */
#define ESMC_MMU_CMD            0x0020 |   \
                                0x0040 |   \
                                0x0080
                                
/* mmu cmds */
#define ESMC_MMU_ALLOC          0x0020    /* get memory from chip memory/256 */
#define ESMC_MMU_NOP            0x0000
#define ESMC_MMU_RESET          0x0040    
#define ESMC_MMU_RX_REMOVE      0x0060    /* remove current RX frame from FIFO */
#define ESMC_MMU_RX_RELEASE     0x0080    /* also release memory associated */
#define ESMC_MMU_TX_RELEASE     0x00A0    /* free packet memory in PNR register */
#define ESMC_MMU_ENQUEUE        0x00C0    /* Enqueue the packet for transmit */
#define ESMC_MMU_TX_RESET       0x00E0    /* reset TX FIFO's */

/* Allocation Result Register */
#define ESMC_ARR_PACKETNUMBER   0x001 |  \
                                0x002 |  \
                                0x004 |  \
                                0x008 |  \
                                0x010
/* unused                       0x020     */
/* unused                       0x040     */
#define ESMC_ARR_FAILED         0x080

/* FIFO Ports Register */
#define ESMC_FIFO_TX_DONE_PACKET_NUMBER   0x0001  | \
                                          0x0002  | \
                                          0x0004  | \
                                          0x0008  | \
                                          0x0010  
/* unused                                 0x0020     */
/* unused                                 0x0040     */
#define ESMC_FIFO_TEMPTY                  0x0080    /* no tx packets queued in TX FIFO  */

#define ESMC_FIFO_RX_PACKET_NUMBER        0x0100  | \
                                          0x0200  | \
                                          0x0400  | \
                                          0x0800  | \
                                          0x1000
/* unused                                 0x2000     */
/* unused                                 0x4000     */
#define ESMC_FIFO_REMPTY                  0x8000    /* no rx packets queued in RX FIFO */



/* Pointer Register - address to be accessed in chip memory */
#define ESMC_PTR_READ       0x2000    /* type of access to follow */
#define ESMC_PTR_AUTOINC    0x4000    /* auto incs. PTR correct amount */
#define ESMC_PTR_RCV        0x8000    /* when set, refers to receive area */

/* Interrupt Detail */
#define ESMC_INT_RCV           0x01
#define    ESMC_INT_TX         0x02    /* set when at least one packet sent */
#define    ESMC_INT_TX_EMPTY   0x04    /* set id TX_FIFO empty */
#define    ESMC_INT_ALLOC      0x08    /* set when MMU allocation is done */
#define    ESMC_INT_RX_OVRN    0x10    /* set when receiver overruns */
#define    ESMC_INT_EPH        0x20    /* Set when EPH handler fires */

#define ESMC_INT_ERCV        0x40    /* early receive */

/* BANK 3 I/O Space mapping */
#ifndef SH_BIG_ENDIAN
#define    ESMC_MULTICAST0        0x0    /* multicast table - WORD 0 */
#define    ESMC_MULTICAST2        0x2    /* multicast table - WORD 1 */
#define    ESMC_MULTICAST4        0x4    /* multicast table - WORD 2 */
#define    ESMC_MULTICAST6        0x6    /* multicast table - WORD 3 */
#define    ESMC_MGMT              0x8
#define    ESMC_REVISION          0xA    /* chip set and revision encoded here */
#define    ESMC_ERCV              0xC    /* early receive register */
#else
#define    ESMC_MULTICAST0        0x2    /* multicast table - WORD 0 */
#define    ESMC_MULTICAST2        0x0    /* multicast table - WORD 1 */
#define    ESMC_MULTICAST4        0x6    /* multicast table - WORD 2 */
#define    ESMC_MULTICAST6        0x4    /* multicast table - WORD 3 */
#define    ESMC_MGMT              0xA
#define    ESMC_REVISION          0x8    /* chip set and revision encoded here */
#define    ESMC_ERCV              0xE    /* early receive register */
#endif /* SH_BIG_ENDIAN */

/* Management Interface Register */
#define    ESMC_MGMT_MDO          0x1 
#define    ESMC_MGMT_MDI          0x2
#define    ESMC_MGMT_MCLK         0x4
#define    ESMC_MGMT_MDOE         0x8 
/* Ask Dan if for completeness sake we list all relevant bits even if defines not used above */

/* Receive frame status word - located at beginning of each received frame*/

#define ESMC_RS_ALGNERR        0x8000    /* frame had alignment error */
#define ESMC_RS_BRODCAST       0x4000    /* receive frame was broadcast */
#define ESMC_RS_BADCRC         0x2000    /* CRC error */
#define ESMC_RS_ODDFRM         0x1000    /* receive frame had odd byte */
#define ESMC_RS_TOOLONG        0x0800    /* longer then 1518 bytes */
#define ESMC_RS_TOOSHORT       0x0400    /* shorter then 64 bytes */
#define ESMC_RS_MULTICAST      0x0001    /* receive frame was multicast */
#define ESMC_RS_ERROR_MASK    (ESMC_RS_ALGNERR | ESMC_RS_BADCRC | ESMC_RS_TOOLONG | ESMC_RS_TOOSHORT) 

/* LAN 91C111 specific: PHY Status Output */

#define PHY_STATUS_OUTPUT      0x12   /* LAN 91C111 specific: Status Output */

#define PHY_STATUS_INT          0x8000 /* Interrupt detect */
#define PHY_STATUS_LNKFAIL      0x4000 /* Link fail detect */
#define PHY_STATUS_LOSSSYNC     0x2000 /* Descrambler loss of synchronization detect */
#define PHY_STATUS_CWRD         0x1000 /* Codeword error */
#define PHY_STATUS_SSD          0x0800 /* Start of stream error */
#define PHY_STATUS_ESD          0x0400 /* End of stream error */
#define PHY_STATUS_RPOL         0x0200 /* Reverse polarity detect */
#define PHY_STATUS_JAB          0x0100 /* Jabber detect */
#define PHY_STATUS_SPDDET       0x0080 /* 100/10 Speed detect */
#define PHY_STATUS_DPLXDET      0x0040 /* Duplex detect */

/* LAN 91C111 specific: PHY Interrupt Mask */

#define PHY_MASK_REG           0x13   /* LAN 91C111 specific: Interrupt Mask */

#define PHY_MASK_INT            0x8000 /* Interrupt mask interrupt detect */
#define PHY_MASK_LNKFAIL        0x4000 /* Interrupt mask link fail detect */
#define PHY_MASK_LOSSSYNC       0x2000 /* Interrupt mask descrambler loss of synchronization detect */
#define PHY_MASK_CWRD           0x1000 /* Interrupt mask codeword error */
#define PHY_MASK_SSD            0x0800 /* Interrupt mask start of stream error */
#define PHY_MASK_ESD            0x0400 /* Interrupt mask end of stream error */
#define PHY_MASK_RPOL           0x0200 /* Interrupt mask reverse polarity detect */
#define PHY_MASK_JAB            0x0100 /* Interrupt mask jabber detect */
#define PHY_MASK_SPDDET         0x0080 /* Interrupt mask 100/10 speed detect */
#define PHY_MASK_DPLXDET        0x0040 /* Interrupt mask duplex detect */

#ifdef __cplusplus
}
#endif

#endif    /* INCesmcEndh */