esmcend.h

基于嵌入式操作系统VxWorks的lan91c111的驱动程序

/* esmcEnd.h - SMSC 91cxxx network interface header */ 

/* Copyright 1984-2004 Wind River Systems, Inc. */

/*
modification history
--------------------
01c,17jan04,jch  Added optional support for emptying and releasing internal
                 FIFO pages in ISR context.
01b,15jan03,bjn  Added support for LAN91C111 device.
01a,28jun02,dnb  mostly copied from if_esmc.h
*/


#ifndef INCesmcEndh
#define INCesmcEndh

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Define ESMC_USE_ISR_COPY to empty and release internal FIFO pages for
 * received frames in ISR context.  The will help keep the FIFO from
 * overflowing, which causes missed frames and transmit failures, at the
 * expense of increased interrupt latency.
 */

#define sysOutByte(addr,data)   (*((UINT8 *) (addr)) = ((UINT8) (data)))
#define sysInByte(addr)         (*((UINT8 *) (addr)))
#define sysOutWord(addr,data)   (*((UINT16 *) (addr)) = ((UINT16) (data)))
#define sysInWord(addr)         (*((UINT16 *) (addr)))
#define sysOutLong(addr,data)   (*((UINT32 *) (addr)) = ((UINT32) (data)))
#define sysInLong(addr)         ((UINT32)(*((UINT16 *) (addr))) | (UINT32)((*((UINT16 *) (addr)) << 16)))
//#define sysInLong(addr)         ((UINT32)(*((UINT16 *) (addr)) << 16) | (UINT32)((*((UINT16 *) (addr)))))

#define ESMC_USE_ISR_COPY

#define DEV_NAME          "esmc"
#define DEV_NAME_LEN      5

#define EADDR_LEN         6
#define ESMC_BUFSIZ       (ETHERMTU + SIZEOF_ETHERHEADER + EADDR_LEN)

#ifdef SH_BIG_ENDIAN
#define ESMC_BANK_SELECT  0x0c
#else
#define ESMC_BANK_SELECT  0x0e
#endif

/* Chip Ids */
#define LAN91C100FD       8 
#define LAN91C111         9

/* BANK 0 I/O Space mapping */

#ifndef SH_BIG_ENDIAN
#define    ESMC_TCR       0x0    /* transmit control register */
#define    ESMC_EPH       0x2    /* EPH status register */
#define    ESMC_RCR       0x4    /* receive control register */
#define    ESMC_COUNTER   0x6    /* counter register */
#define    ESMC_MIR       0x8    /* memory information register */
#define    ESMC_MCR       0xA    /* memory configuration register */
#define    ESMC_RPCR      0xA    /* LAN91C111 specific: Rx/Physical Control Register */
#else
#define    ESMC_TCR       0x2    /* transmit control register */
#define    ESMC_EPH       0x0    /* EPH status register */
#define    ESMC_RCR       0x6    /* receive control register */
#define    ESMC_COUNTER   0x4    /* counter register */
#define    ESMC_MIR       0xA    /* memory information register */
#define    ESMC_MCR       0x8    /* memory configuration register */
#define    ESMC_RPCR      0x8    /* LAN91C111 specific: Rx/Physical Control Register */
#endif

/* Transmit Control Register */
#define ESMC_TCR_TXEN        0x0001    /* transmit enabled when set */ 
#define ESMC_TCR_LOOP        0x0002    /* internal loopback */
#define ESMC_TCR_FORCOL      0x0004    /* force collision, then auto resets */ 
/* unused                    0x0008     */

/* unused                    0x0010     */
/* unused                    0x0020     */
/* unused                    0x0040     */
#define ESMC_TCR_PAD         0x0080    /* pad short frames to 64 bytes */

#define ESMC_TCR_NOCRC       0x0100    /* NOT append CRC to frame if set */
/* unused                    0x0200     */
#define ESMC_TCR_MON_CNS     0x0400    /* monitors the carrier while trans */
#define ESMC_TCR_FDUPLEX     0x0800    /* enable full duplex operation */
#define ESMC_TCR_STP_SQET    0x1000    /* stop trans on signal quality error */
#define ESMC_TCR_EPH_LOOP    0x2000    /* internal loopback at EPH block */
/* unused                    0x4000     */
/* unused                    0x8000     */   


/* EPH Status Register - stores status of last transmitted frame */
/* ## indicates fatal error */
#define ESMC_TS_TX_SUC       0x0001    /* last Transmit was successful */
#define ESMC_TS_SNGLCOL      0x0002    /* single collision detected */
#define ESMC_TS_MULCOL       0x0004    /* multiple collision detected */
#define ESMC_TS_LXT_MULT     0x0008    /* last frame was multicast */

#define ESMC_TS_16COL        0x0010    /* ## 16 collisions reached */
#define ESMC_TS_SQET         0x0020    /* ## signal quality error test */
#define ESMC_TS_LTX_BRD      0x0040    /* last frame was broascast packet */
#define ESMC_TS_TX_DEFR      0x0080    /* transmit deferred - auot cleared */

/* unused                    0x0100     */
#define ESMC_TS_LATCOL       0x0200    /* ## late collision */
#define ESMC_TS_LOST_CARR    0x0400    /* ## lost carrier sense */
#define ESMC_TS_EXC_DEF      0x0800    /* excessive deferal */

#define ESMC_TS_CTR_ROL      0x1000    /* counter rollover */
#define ESMC_TS_RX_OVRN      0x2000    /* on FIFO overrun... */
#define ESMC_TS_LINK_OK      0x4000    /* twisted pair link cond */  
#define ESMC_TS_TXUNRN       0x8000    /* tramsmit under run */


                                     
/* Receive control register */
#define ESMC_RCR_RX_ABORT    0x0001    /* set if receiver overrun */
#define    ESMC_RCR_PRMS     0x0002    /* enable promiscuous mode */
#define ESMC_RCR_ALMUL       0x0004    /* receive all multicast packets */
/* unused                    0x0008     */

/* unused                    0x0010     */
/* unused                    0x0020     */
/* unused                    0x0040     */
/* unused                    0x0080     */

#define ESMC_RCR_RXEN        0x0100    /* ENABLE receiver */  
#define ESMC_RCR_STRIP_CRC   0x0200    /* when set, strips CRC */
#define ESMC_RCR_FILT_CAR    0x4000    /* filter carrier sense 12 bits */ 
#define ESMC_RCR_EPH_RST     0x8000    /* software activated reset */

/* unused                    0x1000     */
/* unused                    0x2000     */
/* unused                    0x4000     */
/* unused                    0x8000     */


/* Memory Information Register */

#define ESMC_MIR_FREE        MIR    /* read at any time for free mem */
#define ESMC_MIR_SIZE        MIR+1    /* determine amount of onchip mem */

/*
 * LAN91C111 specific register: RPCR Receive/Phy Control Register.
 */

#define ESMC_RPCR_SPEED      0x2000
#define ESMC_RPCR_DPLX       0x1000
#define ESMC_RPCR_ANEG       0x0800
#define ESMC_RPCR_LEDA_BS    5             /* Bit shift */
#define ESMC_RPCR_LEDB_BS    2             /* Bit shift */

#define ESMC_RPCR_DEFAULT   ((0 << ESMC_RPCR_LEDA_BS) | (4 << ESMC_RPCR_LEDB_BS))

/* BANK 1 I/O Space mapping */

#ifndef    SH_BIG_ENDIAN
#define    ESMC_CONFIG       0x0    /* configuration register */
#define    ESMC_BASE         0x2    /* base address register */
#define    ESMC_ADDR_0       0x4    /* individual address register 0 */
#define    ESMC_ADDR_1       0x6    /* individual address register 1 */
#define    ESMC_ADDR_2       0x8    /* individual address register 2 */
#define    ESMC_GENERAL      0xA    /* general purpose register */
#define    ESMC_CONTROL      0xC    /* control register */
#else
#define    ESMC_CONFIG       0x2    /* configuration register */
#define    ESMC_BASE         0x0    /* base address register */
#define    ESMC_ADDR_0       0x6    /* individual address register 0 */
#define    ESMC_ADDR_1       0x4    /* individual address register 1 */
#define    ESMC_ADDR_2       0xA    /* individual address register 2 */
#define    ESMC_GENERAL      0x8    /* general purpose register */
#define    ESMC_CONTROL      0xE    /* control register */
#endif

/* Configuration register */
/* unused                     0x0001    */
#define ESMC_INT_SEL_0        0x0002
#define ESMC_INT_SEL_2        0x0004
/* reserved                   0x0008     */

/* reserved                   0x0010     */
/* reserved                   0x0020     */
#define ESMC_CFG_DIS_LINK     0x0040    /* disables link test, TP only */
#define ESMC_CFG_16BIT        0x0080    /* usually auto set   16/8 selection */

#define ESMC_CFG_AUI_SELECT   0x0100    /* when set use AUI */
#define ESMC_CFG_SET_SQLCH    0x0200    /* when set squelch level is 240mV */
#define ESMC_CFG_FULL_STEP    0x0400    /* AUI, use full step signaling */
/* unused                     0x0800     */