📄 ledwater.map.rpt
字号:
; C8_USE_CASC_IN ; OFF ; Untyped ;
; C9_USE_CASC_IN ; OFF ; Untyped ;
; CLK0_COUNTER ; G0 ; Untyped ;
; CLK1_COUNTER ; G0 ; Untyped ;
; CLK2_COUNTER ; G0 ; Untyped ;
; CLK3_COUNTER ; G0 ; Untyped ;
; CLK4_COUNTER ; G0 ; Untyped ;
; CLK5_COUNTER ; G0 ; Untyped ;
; L0_TIME_DELAY ; 0 ; Untyped ;
; L1_TIME_DELAY ; 0 ; Untyped ;
; G0_TIME_DELAY ; 0 ; Untyped ;
; G1_TIME_DELAY ; 0 ; Untyped ;
; G2_TIME_DELAY ; 0 ; Untyped ;
; G3_TIME_DELAY ; 0 ; Untyped ;
; E0_TIME_DELAY ; 0 ; Untyped ;
; E1_TIME_DELAY ; 0 ; Untyped ;
; E2_TIME_DELAY ; 0 ; Untyped ;
; E3_TIME_DELAY ; 0 ; Untyped ;
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; Cyclone ; Untyped ;
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK0 ; PORT_USED ; Untyped ;
; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
; PORT_CLK6 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK7 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK8 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK9 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_INCLK0 ; PORT_USED ; Untyped ;
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
; PORT_ARESET ; PORT_USED ; Untyped ;
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_LOCKED ; PORT_USED ; Untyped ;
; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; C6_TEST_SOURCE ; 0 ; Untyped ;
; C7_TEST_SOURCE ; 0 ; Untyped ;
; C8_TEST_SOURCE ; 0 ; Untyped ;
; C9_TEST_SOURCE ; 0 ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
; WIDTH_CLOCK ; 6 ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Aug 28 20:39:58 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater
Info: Found 2 design units, including 1 entities, in source file ledwater.vhd
Info: Found design unit 1: ledwater-led
Info: Found entity 1: ledwater
Info: Elaborating entity "ledwater" for the top level hierarchy
Warning: Using design file pll20.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: pll20-SYN
Info: Found entity 1: pll20
Info: Elaborating entity "pll20" for hierarchy "pll20:u1"
Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "pll20:u1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "pll20:u1|altpll:altpll_component"
Info: Duplicate registers merged to single register
Info: Duplicate register "cnt[32]" merged to single register "Ram0~15"
Info: Duplicate register "cnt[33]" merged to single register "Ram0~16"
Info: Duplicate register "cnt[34]" merged to single register "Ram0~17"
Info: Duplicate register "cnt[35]" merged to single register "Ram0~18"
Info: Duplicate register "cnt[36]" merged to single register "Ram0~19"
Info: Duplicate register "cnt[37]" merged to single register "Ram0~20"
Info: Implemented 130 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 11 output pins
Info: Implemented 115 logic cells
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 136 megabytes of memory during processing
Info: Processing ended: Tue Aug 28 20:40:12 2007
Info: Elapsed time: 00:00:14
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