pll20_waveforms.html

来自「FPGA下的DDS程序的编写,VHDL语言,」· HTML 代码 · 共 14 行

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14 行

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<title>Sample Waveforms for pll20.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file pll20.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll20.vhd. The design pll20.vhd has Cyclone AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 50000 ps. Output port LOCKED will go high when the PLL locks to the input clock. </P>
<CENTER><img src=pll20_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3>When input port ARESET is asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted. </P>
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