ledwater.fit.qmsg

FPGA下的DDS程序的编写,VHDL语言,

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pll20:u1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"pll20:u1\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } { "pll20.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/pll20.vhd" 136 0 0 } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 137 0 0 } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "key_data\[0\] " "Warning: Node \"key_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_data\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "key_data\[1\] " "Warning: Node \"key_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_data\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "key_data\[2\] " "Warning: Node \"key_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_data\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "key_data\[3\] " "Warning: Node \"key_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_data\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "key_int " "Warning: Node \"key_int\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_int" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.168 ns register register " "Info: Estimated most critical path is register to register delay of 3.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LAB_X16_Y11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y11; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.575 ns) 1.036 ns cnt\[0\]~165COUT1 2 COMB LAB_X16_Y11 2 " "Info: 2: + IC(0.461 ns) + CELL(0.575 ns) = 1.036 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'cnt\[0\]~165COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.036 ns" { cnt[0] cnt[0]~165COUT1 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.116 ns cnt\[1\]~164COUT1 3 COMB LAB_X16_Y11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.116 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'cnt\[1\]~164COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { cnt[0]~165COUT1 cnt[1]~164COUT1 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.196 ns cnt\[2\]~163COUT1 4 COMB LAB_X16_Y11 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.196 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'cnt\[2\]~163COUT1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { cnt[1]~164COUT1 cnt[2]~163COUT1 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.454 ns cnt\[3\]~162 5 COMB LAB_X16_Y11 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.454 ns; Loc. = LAB_X16_Y11; Fanout = 6; COMB Node = 'cnt\[3\]~162'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { cnt[2]~163COUT1 cnt[3]~162 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.590 ns cnt\[8\]~157 6 COMB LAB_X16_Y11 6 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.590 ns; Loc. = LAB_X16_Y11; Fanout = 6; COMB Node = 'cnt\[8\]~157'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { cnt[3]~162 cnt[8]~157 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.726 ns cnt\[13\]~152 7 COMB LAB_X16_Y10 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.726 ns; Loc. = LAB_X16_Y10; Fanout = 6; COMB Node = 'cnt\[13\]~152'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { cnt[8]~157 cnt[13]~152 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.862 ns cnt\[18\]~147 8 COMB LAB_X16_Y10 6 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 1.862 ns; Loc. = LAB_X16_Y10; Fanout = 6; COMB Node = 'cnt\[18\]~147'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { cnt[13]~152 cnt[18]~147 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.998 ns cnt\[23\]~142 9 COMB LAB_X16_Y9 6 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 1.998 ns; Loc. = LAB_X16_Y9; Fanout = 6; COMB Node = 'cnt\[23\]~142'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { cnt[18]~147 cnt[23]~142 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.134 ns cnt\[28\]~137 10 COMB LAB_X16_Y9 6 " "Info: 10: + IC(0.000 ns) + CELL(0.136 ns) = 2.134 ns; Loc. = LAB_X16_Y9; Fanout = 6; COMB Node = 'cnt\[28\]~137'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { cnt[23]~142 cnt[28]~137 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.270 ns Ram0~1556 11 COMB LAB_X16_Y8 4 " "Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 2.270 ns; Loc. = LAB_X16_Y8; Fanout = 4; COMB Node = 'Ram0~1556'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { cnt[28]~137 Ram0~1556 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 3.168 ns Ram0~20 12 REG LAB_X16_Y8 21 " "Info: 12: + IC(0.000 ns) + CELL(0.898 ns) = 3.168 ns; Loc. = LAB_X16_Y8; Fanout = 21; REG Node = 'Ram0~20'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.898 ns" { Ram0~1556 Ram0~20 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.707 ns ( 85.45 % ) " "Info: Total cell delay = 2.707 ns ( 85.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns ( 14.55 % ) " "Info: Total interconnect delay = 0.461 ns ( 14.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { cnt[0] cnt[0]~165COUT1 cnt[1]~164COUT1 cnt[2]~163COUT1 cnt[3]~162 cnt[8]~157 cnt[13]~152 cnt[18]~147 cnt[23]~142 cnt[28]~137 Ram0~1556 Ram0~20 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X27_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 28 20:40:33 2007 " "Info: Processing ended: Tue Aug 28 20:40:33 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/DDFS_PLL_10DA_with51/ledwater.fit.smsg " "Info: Generated suppressed messages file E:/DDFS_PLL_10DA_with51/ledwater.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}