ledwater.map.qmsg

FPGA下的DDS程序的编写,VHDL语言,

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 28 20:39:58 2007 " "Info: Processing started: Tue Aug 28 20:39:58 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledwater.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ledwater.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ledwater-led " "Info: Found design unit 1: ledwater-led" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ledwater " "Info: Found entity 1: ledwater" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ledwater " "Info: Elaborating entity \"ledwater\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pll20.vhd 2 1 " "Warning: Using design file pll20.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll20-SYN " "Info: Found design unit 1: pll20-SYN" {  } { { "pll20.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/pll20.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pll20 " "Info: Found entity 1: pll20" {  } { { "pll20.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/pll20.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll20 pll20:u1 " "Info: Elaborating entity \"pll20\" for hierarchy \"pll20:u1\"" {  } { { "ledwater.vhd" "u1" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 137 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 454 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll20:u1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"pll20:u1\|altpll:altpll_component\"" {  } { { "pll20.vhd" "altpll_component" { Text "E:/DDFS_PLL_10DA_with51/pll20.vhd" 136 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pll20:u1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"pll20:u1\|altpll:altpll_component\"" {  } { { "pll20.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/pll20.vhd" 136 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt\[32\] Ram0~15 " "Info: Duplicate register \"cnt\[32\]\" merged to single register \"Ram0~15\"" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt\[33\] Ram0~16 " "Info: Duplicate register \"cnt\[33\]\" merged to single register \"Ram0~16\"" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt\[34\] Ram0~17 " "Info: Duplicate register \"cnt\[34\]\" merged to single register \"Ram0~17\"" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt\[35\] Ram0~18 " "Info: Duplicate register \"cnt\[35\]\" merged to single register \"Ram0~18\"" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt\[36\] Ram0~19 " "Info: Duplicate register \"cnt\[36\]\" merged to single register \"Ram0~19\"" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt\[37\] Ram0~20 " "Info: Duplicate register \"cnt\[37\]\" merged to single register \"Ram0~20\"" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "130 " "Info: Implemented 130 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "115 " "Info: Implemented 115 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Allocated 136 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 28 20:40:12 2007 " "Info: Processing ended: Tue Aug 28 20:40:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}