ledwater.fit.summary

来自「FPGA下的DDS程序的编写,VHDL语言,」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Tue Aug 28 20:40:33 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : ledwater
Top-level Entity Name : ledwater
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 114 / 2,910 ( 4 % )
Total pins : 14 / 104 ( 13 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 1 / 1 ( 100 % )