ledwater.tan.summary

FPGA下的DDS程序的编写,VHDL语言,

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 0.828 ns
From           : sda
To             : reg32[31]
From Clock     : --
To Clock       : sck
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.778 ns
From           : Ram0~16
To             : output[1]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.776 ns
From           : sda
To             : reg32[31]
From Clock     : --
To Clock       : sck
Failed Paths   : 0

Type           : Clock Setup: 'pll20:u1|altpll:altpll_component|_clk0'
Slack          : 1.996 ns
Required Time  : 180.02 MHz ( period = 5.555 ns )
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : cnt[0]
To             : Ram0~19
From Clock     : pll20:u1|altpll:altpll_component|_clk0
To Clock       : pll20:u1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'sck'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : reg32[30]
To             : reg32[29]
From Clock     : sck
To Clock       : sck
Failed Paths   : 0

Type           : Clock Hold: 'pll20:u1|altpll:altpll_component|_clk0'
Slack          : 1.323 ns
Required Time  : 180.02 MHz ( period = 5.555 ns )
Actual Time    : N/A
From           : cnt[7]
To             : cnt[7]
From Clock     : pll20:u1|altpll:altpll_component|_clk0
To Clock       : pll20:u1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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