ledwater.vhd

FPGA下的DDS程序的编写,VHDL语言,

--f0=fr*FSW/2^37
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ledwater is	--实体名
	port(	clk:	in std_logic;	--时钟
			sda:in std_logic;
			sck:in std_logic;
			
			DAC_CLK: out std_logic;	--DAC时钟
			output:out integer range 0 to 1023);--std_logic_vector(7 downto 0 ));	--输出
end entity ledwater;

--architecture led of ledwater is
--begin
--	output<="01010101";
--end led;

architecture led of ledwater is
	component pll20
		PORT(inclk0:in std_logic := '0';
				c0: out std_logic);
	end component;
	signal cnt:std_logic_vector(37 downto 0);
	--signal key_cnt:INTEGER RANGE 0 to 10000000;--时间为500ms
	--signal FSW : integer range 0 to 67108863 :=1000;	--频率控制字
	signal reg32:std_logic_vector(31 downto 0);
	
	signal FSW:std_logic_vector(31 downto 0):="00000000000000111111111111111111";
	  --signal FSW:std_logic_vector(31 downto 0):="00000000000011111111111111111111";

	--signal a:integer rang 0 to 15;
	signal pllclk:std_logic;
	begin
		process(cnt)
			begin
				
				case cnt(37 downto 32) is
					
					when "000000" => output <=16#1ff#;
					when "000001" => output <=16#231#;
					when "000010" => output <=16#262#;
					when "000011" => output <=16#293#;
					when "000100" => output <=16#2c2#;
					when "000101" => output <=16#2ef#;
					when "000110" => output <=16#31a#;
					when "000111" => output <=16#343#;
					when "001000" => output <=16#368#;
					when "001001" => output <=16#389#;
					when "001010" => output <=16#3a7#;
					when "001011" => output <=16#3c1#;
					when "001100" => output <=16#3d6#;
					when "001101" => output <=16#3e7#;
					when "001110" => output <=16#3f4#;
					when "001111" => output <=16#3fb#;
					when "010000" => output <=16#3fd#;
					when "010001" => output <=16#3fb#;
					when "010010" => output <=16#3f4#;
					when "010011" => output <=16#3e8#;
					when "010100" => output <=16#3d7#;
					when "010101" => output <=16#3c1#;
					when "010110" => output <=16#3a8#;
					when "010111" => output <=16#38a#;
					when "011000" => output <=16#368#;
					when "011001" => output <=16#343#;
					when "011010" => output <=16#31b#;
					when "011011" => output <=16#2f0#;
					when "011100" => output <=16#2c3#;
					when "011101" => output <=16#294#;
					when "011110" => output <=16#263#;
					when "011111" => output <=16#231#;
					when "100000" => output <=16#1ff#;
					when "100001" => output <=16#1cd#;
					when "100010" => output <=16#19c#;
					when "100011" => output <=16#16b#;
					when "100100" => output <=16#13c#;
					when "100101" => output <=16#10e#;
					when "100110" => output <=16#0e3#;
					when "100111" => output <=16#0bb#;
					when "101000" => output <=16#096#;
					when "101001" => output <=16#074#;
					when "101010" => output <=16#056#;
					when "101011" => output <=16#03c#;
					when "101100" => output <=16#027#;
					when "101101" => output <=16#016#;
					when "101110" => output <=16#00a#;
					when "101111" => output <=16#002#;
					when "110000" => output <=16#000#;
					when "110001" => output <=16#002#;
					when "110010" => output <=16#009#;
					when "110011" => output <=16#015#;
					when "110100" => output <=16#026#;
					when "110101" => output <=16#03b#;
					when "110110" => output <=16#055#;
					when "110111" => output <=16#073#;
					when "111000" => output <=16#094#;
					when "111001" => output <=16#0b9#;
					when "111010" => output <=16#0e1#;
					when "111011" => output <=16#10c#;
					when "111100" => output <=16#13a#;
					when "111101" => output <=16#169#;
					when "111110" => output <=16#199#;
					when "111111" => output <=16#1cb#;
					when others => null;
					
								
					
				end case;
			end process ;
		process(pllclk)
			begin
			--	if clr='1' then FSW<=1;key_cnt<=0;
				--end if;
				if pllclk'event and pllclk='1'	then cnt <= cnt+FSW;
				--if DAC_CLK='0'	then DAC_CLK<='1'; else DAC_CLK<='0';
				
				end if;				
				DAC_CLK<=pllclk;	--DAC时钟
				
				--if key_cnt = 9999999 then 
				--	key_cnt<=0;
						--if key = '1' then
						--	FSW<=16777216;
							--else FSW<=65535;
						--end if;
				--end if;
			end process ;
		process(sck)
		begin			
			if sck'event and sck='0' then
				reg32(30 downto 0)<=reg32(31 downto 1);
				reg32(31)<=sda;
			end if;
		end process;	
		FSW<=reg32;
		u1:pll20 port map(inclk0 => clk,c0 => pllclk);	
end led;