📄 f243pwm2.asm
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;=====================================================================================================================
; File name: F243PWM2.ASM
;
; Originator: Digital Control Systems Group
; Texas Instruments
; Description:
; This file contains source for the Full Compare PWM drivers for the F243
; Applicability of these functions is indicated in the Table 1
;=====================================================================================
; History:
;-------------------------------------------------------------------------------------
; 9-15-2000 Release Rev 1.0
;================================================================================
; T A B L E 1
;================================================================================
; Function Name | Applicability
;================================================================================
; | F240 | F241| F243 | LF2402 | LF2406 | LF2407
; | | | | | |
; F243_PWM_Update | | Y | Y | | |
;================================================================================
;================================================================================
; Routine Name: PWM Update Routine Routine Type: C Callable
;
; Description:
;
; Sine Module
;
; C prototype : int F243_PWM_Update(PWMGEN *p)
;================================================================================
;
; History:
; __________________________________________________________________________
; Date of Mod | DESCRIPTION
; ------------|-----------------------------------------------------------
; |
; |
; |
; |
;================================================================================
; Definition of the argument structure.
; struct _PWMGEN_struct
;{
; int period, period_mod ;
; int duty_cycle1, duty_cycle2, duty_cycle3; /* Duty cycle ratios */
; int (*init)(); /* Initialization func pointer */
; int (*update)(); /* Update function */
;
;
;
;
.def _F243_PWM_Update
.include ..\include\x24x.h
_F243_PWM_Update:
__F243_PWM_Update_framesize .set 0002h
POPD *+
SAR AR0,*+
SAR AR1,*
LARK AR0,__F243_PWM_Update_framesize
LAR AR0,*0+,AR0
;================================================================================
SBRK #3 ; Point to ARG1 (in this case period)
; AR0=(FP0)-3
LAR AR2,* ; get pointer to ARG in AR2.
; This first arg is the pointer to the structure,
; and by LAR AR2,* we get that pointer in AR2. As a result AR2 now
; points to PWMGEN_struct, as defined above.
;--------------------------------------------------------------------------------
LAR AR3,#CMPR1 ; point AR3 to CMPR1.
;--------------------------------------------------------------------------------
MAR *,AR0
ADRK #3 ; Point AR0 back to FP0.
;--------------------------------------------------------------------------------
MAR *,AR2 ; Make AR2 the current ARP.
; AR2 now points to period.
;--------------------------------------------------------------------------------
LT *+ ; Get period in TREG and point AR2 to
; the next loc which is period_mod.
;--------------------------------------------------------------------------------
MPY *+,AR0 ; multiply by period_mod.
; also increment AR2 to pt to duty_cycle1
; set ARP=AR0 -> FP0.
;--------------------------------------------------------------------------------
SPM 1 ; set appropriate product mode.
;--------------------------------------------------------------------------------
PAC
; ACCH now contains the modified
; period (Q0).
;--------------------------------------------------------------------------------
SACH *+ ; FR0 now contains the modified period.
;--------------------------------------------------------------------------------
SFR ; divide by 2.
; =prd.
;--------------------------------------------------------------------------------
SACH * ; FR1 now contains the modified period/2.
; prd
;--------------------------------------------------------------------------------
LT *,AR2 ; Get modified prd in TREG and ARP=AR2.
;--------------------------------------------------------------------------------
MPY *+,AR0 ; form prd*duty_cycle1 .
; inc AR2 to point to duty_cycle2.
; also ARP=AR0.
;--------------------------------------------------------------------------------
PAC ; get cmpr1_value in ACCH. (Q0 in ACCH).
;--------------------------------------------------------------------------------
ADDH *,AR3 ; ACCH= prd*duty_cycle1 + prd.
;--------------------------------------------------------------------------------
SACH *+,AR2 ; store cmpr1_value in CMPR1.
; also incr AR3 to point to CMPR2,
; and ARP=AR2.
;--------------------------------------------------------------------------------
MPY *+,AR0 ; form prd*duty_cycle2.
; inc AR2 to point to duty_cycle3.
; also ARP=AR0.
;--------------------------------------------------------------------------------
PAC ; get cmpr2_value in ACCH. (Q0 in ACCH).
;--------------------------------------------------------------------------------
ADDH *,AR3 ; ACCH= prd*duty_cycle2 + prd.
;--------------------------------------------------------------------------------
SACH *+,AR2 ; store cmpr2_value in CMPR2.
; also incr AR3 to point to CMPR3,
; and ARP=AR2.
;--------------------------------------------------------------------------------
MPY *,AR0 ; form prd*duty_cycle3.
; also ARP=AR0.
;--------------------------------------------------------------------------------
PAC ; get cmpr3_value in ACCH. (Q0 in ACCH).
;--------------------------------------------------------------------------------
ADDH *-,AR3 ; ACCH= prd*duty_cycle3 + prd.
; decrement AR0 to pt to modified period.
;--------------------------------------------------------------------------------
SACH *,AR0 ; store cmpr3_value in CMPR3.
; and ARP=AR0.
;--------------------------------------------------------------------------------
LAR AR3,#T1PR ; point AR3 to T1 period register.
;--------------------------------------------------------------------------------
LACC *,AR3 ; get FR0 = modified_period.
;--------------------------------------------------------------------------------
SACL *,AR1 ; store modified period in T1PR.
; ARP=AR1 for return.
;================================================================================
SPM 0 ; restore compiler's product mode.
;--------------------------------------------------------------------------------
SBRK #(__F243_PWM_Update_framesize+1)
LAR AR0,*-
PSHD *
RET
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