📄 f07ilvd2.asm
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;=====================================================================================================================
; File name: F07ILVD2.ASM
;
; Originator: Digital Control Systems Group
; Texas Instruments
; Description:
; This file contains source for a the F2407 Two leg current measurement
; and DC-bus measurement driver.
;=====================================================================================
; History:
;-------------------------------------------------------------------------------------
; 9-15-2000 Release Rev 1.0
;================================================================================
;
; Applicability: F2407 : Peripheral Dependant
; ____________________
;
;================================================================================
; Routine Name: Generic function. Routine Type: C Callable
;
; Description:
;
; C prototype : int F2407_ileg2_dcbus_drv_read(ILEG2DCBUSMEAS *p)
;
;
; typedef struct { int Imeas_a_gain; /* Parameter: gain for Ia (Q13) */
; int Imeas_a_offset; /* Parameter: offset for Ia (Q15) */
; int Imeas_a; /* Output: measured Ia (Q15) */
; int Imeas_b_gain; /* Parameter: gain for Ib (Q13) */
; int Imeas_b_offset; /* Parameter: offset for Ib (Q15) */
; int Imeas_b; /* Output: measured Ib (Q15) */
; int Vdc_meas_gain; /* Parameter: gain for Vdc (Q13) */
; int Vdc_meas_offset; /* Parameter: offset for Vdc (Q15) */
; int Vdc_meas; /* Output: measured Vdc (Q15) */
; int Imeas_c; /* Output: computed Ic (Q15) */
; int Ch_sel; /* Parameter: ADC channel selection */
; int (*init)(); /* Pointer to the init function */
; int (*read)(); /* Pointer to the read function */
; } ILEG2DCBUSMEAS;
;
; Frame Usage Details:
; step | a | b | c | d
;____________|_____________|______________|______________|_____________
; FR0 | Imeas_a | Imeas_b | Vdc_meas |
;
; Note: FR0 keeps the measured variables in Q15 before doing gain & offset.
;
;================================================================================
.def _F2407_ileg2_dcbus_drv_read
;================================================================================
.include ..\include\x240x.h
;================================================================================
__F2407_ileg2_dcbus_drv_read_framesize .set 0001h
;================================================================================
_F2407_ileg2_dcbus_drv_read:
POPD *+ ; Keep return address
SAR AR0,*+ ; Keep old frame pointer (FP)
SAR AR1,* ; Keep old stack pointer (SP)
LARK AR0,__F2407_ileg2_dcbus_drv_read_framesize ; Load AR0 with frame size
LAR AR0,*0+,AR0 ; AR0->FP0 (new FP), ARP=AR0
;================================================================================
SBRK #3 ; ARP=AR0, AR0->FR0-3 (1st argument)
;--------------------------------------------------------------------------------
LAR AR2,* ; ARP=AR0, AR0->Imeas_a_gain, AR2->Imeas_a_gain
;--------------------------------------------------------------------------------
ADRK #3 ; ARP=AR0, AR0->FR0, AR2->Imeas_a_gain
;--------------------------------------------------------------------------------
MAR *,AR3 ; ARP=AR0, AR0->FR0, AR2->Imeas_a_gain, ARP=AR3
;----------------------------------------------------------------------------------
SETC SXM ; Turn sign extension mode on
; ARP=AR3, AR0->FR0, AR2->Imeas_a_gain
;----------------------------------------------------------------------------------
SETC OVM ; Set overflow mode
; ARP=AR3, AR0->FR0, AR2->Imeas_a_gain
;----------------------------------------------------------------------------------
SPM 0 ; Reset product mode
; ARP=AR3, AR0->FR0, AR2->Imeas_a_gain
;----------------------------------------------------------------------------------
LAR AR3,#ADCTRL2
; ARP=AR3, AR0->FR0, AR2->Imeas_a_gain, AR3->ADC_CNTL2
;--------------------------------------------------------------------------------
WAIT BIT *,BIT12 ; poll ADC Flag to wait for compl. of conv.
; ARP=AR3, AR0->FR0, AR2->Imeas_a_gain, AR3->ADC_CNTL2
;--------------------------------------------------------------------------------
BCND WAIT,TC ; Loop on the ADC Flag for completion (check SEQ_BSY bit)
; ARP=AR3, AR0->FR0, AR2->Imeas_a_gain, AR3->ADC_CNTL2
;--------------------------------------------------------------------------------
ADRK #7 ; ARP=AR3, AR0->FR0, AR2->Imeas_a_gain, AR3->RESULT0
;--------------------------------------------------------------------------------
LACC *,AR0 ; ACC = ADC_RESULT0 (raw data)
; ARP=AR3, AR0->FR0, AR2->Imeas_a_gain, AR3->RESULT0, ARP=AR0
;--------------------------------------------------------------------------------
XOR #8000h ; Convert result to Q15 (bipolar signal)
; ARP=AR0, AR0->FR0, AR2->Imeas_a_gain, AR3->RESULT0
;--------------------------------------------------------------------------------
SACL * ; FR0 = Imeas_a (Q15)
; ARP=AR0, AR0->FR0, AR2->Imeas_a_gain, AR3->RESULT0
;--------------------------------------------------------------------------------
LT *,AR2 ; TREG = Imeas_a (Q15)
; ARP=AR0, AR0->FR0, AR2->Imeas_a_gain, AR3->RESULT0, ARP=AR2
;--------------------------------------------------------------------------------
MPY *+ ; PREG = Imeas_a_gain*Imeas_a (Q28)
; ARP=AR2, AR0->FR0, AR2->Imeas_a_offset, AR3->RESULT0
;--------------------------------------------------------------------------------
PAC ; ACC = Imeas_a_gain*Imeas_a (Q28)
; ARP=AR2, AR0->FR0, AR2->Imeas_a_offset, AR3->RESULT0
;--------------------------------------------------------------------------------
ADD *+,13 ; ACC = Imeas_a_gain*Imeas_a + Imeas_a_offset (Q28)
; ARP=AR2, AR0->FR0, AR2->Imeas_a, AR3->RESULT0
;--------------------------------------------------------------------------------
NEG ; Positive direction, current flows to motor
; ARP=AR2, AR0->FR0, AR2->Imeas_a, AR3->RESULT0
;--------------------------------------------------------------------------------
SACH *+,3,AR3 ; Imeas_a = Imeas_a_gain*Imeas_a + Imeas_a_offset (Q15)
; ARP=AR2, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT0, ARP=AR3
;--------------------------------------------------------------------------------
ADRK #1 ; ARP=AR3, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1
;--------------------------------------------------------------------------------
LACC *,AR0 ; ACC = ADC_RESULT1 (raw data)
; ARP=AR3, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1, ARP=AR0
;--------------------------------------------------------------------------------
XOR #8000h ; Convert result to Q15 (bipolar signal)
; ARP=AR0, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1
;--------------------------------------------------------------------------------
SACL * ; FR0 = Imeas_b (Q15)
; ARP=AR0, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1
;--------------------------------------------------------------------------------
LT *,AR2 ; TREG = Imeas_b (Q15)
; ARP=AR0, AR0->FR0, AR2->Imeas_b_gain, AR3->RESULT1, ARP=AR2
;--------------------------------------------------------------------------------
MPY *+ ; PREG = Imeas_b_gain*Imeas_b (Q28)
; ARP=AR2, AR0->FR0, AR2->Imeas_b_offset, AR3->RESULT1
;--------------------------------------------------------------------------------
PAC ; ACC = Imeas_b_gain*Imeas_b (Q28)
; ARP=AR2, AR0->FR0, AR2->Imeas_b_offset, AR3->RESULT1
;--------------------------------------------------------------------------------
ADD *+,13 ; ACC = Imeas_b_gain*Imeas_b + Imeas_b_offset (Q28)
; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT1
;--------------------------------------------------------------------------------
NEG ; Positive direction, current flows to motor
; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT1
;--------------------------------------------------------------------------------
SACH *+,3,AR3 ; Imeas_b = Imeas_b_gain*Imeas_b + Imeas_b_offset (Q15)
; ARP=AR2, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT1, ARP=AR3
;--------------------------------------------------------------------------------
ADRK #1 ; ARP=AR3, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2
;--------------------------------------------------------------------------------
LACC *,AR0 ; ACC = ADC_RESULT2 (raw data)
; ARP=AR3, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2, ARP=AR0
;--------------------------------------------------------------------------------
SFR ; Convert result to Q15 (unipolar signal)
; ARP=AR0, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2
;-------------------------------------------------------------------------------
AND #7FFFh ; Convert result to Q15 (unipolar signal)
; ARP=AR0, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2
;-------------------------------------------------------------------------------
SACL * ; FR0 = Vdc_meas (Q15)
; ARP=AR0, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2
;--------------------------------------------------------------------------------
LT *,AR2 ; TREG = Vdc_meas (Q15)
; ARP=AR0, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2, ARP=AR2
;--------------------------------------------------------------------------------
MPY *+ ; PREG = Vdc_meas_gain*Vdc_meas (Q28)
; ARP=AR2, AR0->FR0, AR2->Vdc_meas_gain, AR3->RESULT2
;--------------------------------------------------------------------------------
PAC ; ACC = Vdc_meas_gain*Vdc_meas (Q28)
; ARP=AR2, AR0->FR0, AR2->Vdc_meas_offset, AR3->RESULT2
;--------------------------------------------------------------------------------
ADD *+,13 ; ACC = Vdc_meas_gain*Vdc_meas + Vdc_meas_offset (Q28)
; ARP=AR2, AR0->FR0, AR2->Vdc_meas, AR3->RESULT2
;-------------------------------------------------------------------------------
SACH *,3 ; Vdc_meas = Vdc_meas_gain*Vdc_meas + Vdc_meas_offset (Q15)
; ARP=AR2, AR0->FR0, AR2->Vdc_meas, AR3->RESULT2
;-------------------------------------------------------------------------------
SBRK #6 ; ARP=AR2, AR0->FR0, AR2->Imeas_a, AR3->RESULT2
;--------------------------------------------------------------------------------
LACC * ; ACC = Imeas_a (Q15)
; ARP=AR2, AR0->FR0, AR2->Imeas_a, AR3->RESULT2
;-------------------------------------------------------------------------------
ADRK #3 ; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT2
;-------------------------------------------------------------------------------
ADD * ; ACC = Imeas_a + Imeas_b (Q15)
; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT2
;-------------------------------------------------------------------------------
NEG ; ACC = -(Imeas_a + Imeas_b) (Q15)
; ARP=AR2, AR0->FR0, AR2->Imeas_b, AR3->RESULT2
;-------------------------------------------------------------------------------
ADRK #4 ; ARP=AR2, AR0->FR0, AR2->Imeas_c, AR3->RESULT2
;-------------------------------------------------------------------------------
SACL *,AR1 ; Imeas_c = -(Imeas_a + Imeas_b) (Q15)
; ARP=AR2, AR0->FR0, AR2->Imeas_c, AR3->RESULT2, ARP=AR1
;-------------------------------------------------------------------------------
_F2407_ileg2_dcbus_drv_read_exit:
;MAR *,AR1 ; can be removed if this condition is met on
; ; every path to this code. (i.e., ARP=AR1 here)
SBRK #(__F2407_ileg2_dcbus_drv_read_framesize+1)
LAR AR0,*-
PSHD *
RET
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